HYB18T512160BF-2.5 Qimonda, HYB18T512160BF-2.5 Datasheet - Page 29

• Manufacturer Part Number: HYB18T512160BF-2.5
• Description: IC DDR2 SDRAM 512MBIT 84TFBGA
• Manufacturer: Qimonda

Specifications of HYB18T512160BF-2.5

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1016-2

5.4
This chapter describes the Output Buffer Characteristics.
1)
2) The values of
3)
1)
1)
2) Impedance measurement condition for output source dc current:
3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage.
4) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the
5) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured from AC to AC.
6) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included in
7) DRAM output Slew Rate specification applies to 400, 533 and 667 MT/s speed bins.
Rev. 1.2, 2007-11
03292006-YBYM-WG0Z
Symbol
I
I
Symbol
V
V
V
Symbol Description
—
—
—
S
OH
OL
OUT
OH
OL
OTR
V
plus a noise margin and
shifting the desired driver operating points along 21 Ohm load line to define a convenient current for measurement.
V
assumes that
additional series resistor of 20 Ohm this translates into a minimum requirement of 603 mV swing relative to
mA × 45 Ohm = 603 mV).
V
ohms for values of
V
DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18
conditions.
This is verified by design and characterization but not subject to production test.
specification.
The SSTL_18 test load has a 20 Ohm series resistor additionally to the 25 Ohm termination resistor into
DDQ
DDQ
DDQ
OUT
= –280 mV;
= 1.7 V;
= 1.7 V;
= 1.8 V
Output Impedance
Pull-up / Pull down mismatch
Output Impedance step size for OCD calibration
Output Slew Rate
Parameter
Minimum Required Output Pull-up
Maximum Required Output Pull-down
Output Timing Measurement Reference Level
±
I
V
V
±
Parameter
Output Minimum Source DC Current
Output Minimum Sink DC Current
OH(dc)
0.1 V;
OUT
OUT
335 mV must be developed across the effectively 25 Ohm termination resistor (13.4 mA × 25 Ohm = 335 mV). With an
V
V
OUT
= 1.42 V. (
= 280 mV.
Output Buffer Characteristics
and
OUT
V
/
DD
I
I
between
V
OL(dc)
OL
IL.MAX
= 1.8 V
must be less than 23.4 Ohms for values of
V
are based on the conditions given in
V
OUT
minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by
OUT
V
±
–
DDQ
/
V
0.1 V
I
DDQ
OL
and
must be less than 21 Ohm for values of
) /
I
V
OH
DDQ
must be less than 21 Ω for values of
– 280 mV. Impedance measurement condition for output sink dc current:
V
29
DDQ
1)
Min.
0
0
1.5
and
= 1.7 V,
SSTL_18
–13.4
13.4
V
OUT
3)
. They are used to test drive current capability to ensure
between 0 V and 280 mV.
V
OUT
V
Nominal
—
—
—
OUT
= 1420 mV; (
V
512-Mbit Double-Data-Rate-Two SDRAM
0.5 ×
SSTL_18
V
V
OUT
between 0 V and 280 mV.
TT
TT
SSTL_18 Output AC Test Conditions
between
SSTL_18 Output DC Current Drive
+ 0.603
– 0.603
V
DDQ
Max.
4
1.5
5.0
V
OCD Default Characteristics
OUT
V
Unit
mA
mA
DDQ
–
±
V
0.75 Ohms under nominal
HYB18T512[40/80/16]0BF
DDQ
and
V
V
TT
) /
TT
. The SSTL_18 definition
V
I
, at the ouput device (13.4
DDQ
OH
Unit
Ω
Ω
Ω
V / ns
Internet Data Sheet
t
must be less than 23.4
Unit
V
V
V
DQSQ
– 280 mV.
TABLE 26
TABLE 27
TABLE 28
and
Notes
1)2)
2)3)
V
t
DDQ
QHS
Notes
1)2)
1)2)3)
4)
1)5)6)7)
Note
1)
1)
= 1.7 V;
V
IH.MIN
.