HYB18T512160BF-2.5 Qimonda, HYB18T512160BF-2.5 Datasheet - Page 55

• Manufacturer Part Number: HYB18T512160BF-2.5
• Description: IC DDR2 SDRAM 512MBIT 84TFBGA
• Manufacturer: Qimonda

Specifications of HYB18T512160BF-2.5

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1016-2

List of Illustrations
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Rev. 1.2, 2007-11
03292006-YBYM-WG0Z
Configuration for ×4 Components, TFBGA-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Configuration for ×8 Components, TFBGA-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Configuration for ×16 components, TFBGA-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Single-ended AC Input Test Conditions Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . 32
Method for Calculating Transitions and Endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Differential Input Waveform Timing - t
Differential Input Waveform Timing - t
Package Outline PG-TFBGA-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Package Outline PG-TFBGA-84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
DS
lS
and t
and t
lH
DH
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
55
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512[40/80/16]0BF
Internet Data Sheet