C8051F005DK Silicon Laboratories Inc, C8051F005DK Datasheet - Page 152

• Manufacturer Part Number: C8051F005DK
• Description: DEV KIT FOR F005/006/007
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F005DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F01x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F005
• Silicon Family Name: C8051F00x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F005/006/007
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1188

19.3.
Timer 3 is a 16-bit timer formed by the two 8-bit SFRs, TMR3L (low byte) and TMR3H (high byte). The input for
Timer 3 is the system clock (divided by either one or twelve as specified by the Timer 3 Clock Select bit T3M in the
Timer 3 Control Register TMR3CN). Timer 3 is always configured as an auto-reload timer, with the reload value
held in the TMR3RLL (low byte) and TMR3RLH (high byte) registers. Timer 3 can be used to start an ADC Data
Conversion, for SMBus timing (see Section 16.5), or as a general-purpose timer. Timer 3 does not have a counter
mode.
SYSCLK
Bit7:
Bits6-3: UNUSED. Read = 0000b, Write = don’t care.
Bit2:
Bit1:
Bit0:
R/W
TF3
Bit7
Timer 3
Set by hardware when Timer 3 overflows from 0xFFFF to 0x0000. When the Timer 3
interrupt is enabled, setting this bit causes the CPU to vector to the Timer 3 Interrupt
service routine. This bit is not automatically cleared by hardware and must be cleared by
software.
TR3: Timer 3 Run Control.
This bit enables/disables Timer 3.
0: Timer 3 disabled.
1: Timer 3 enabled.
T3M: Timer 3 Clock Select.
This bit controls the division of the system clock supplied to Counter/Timer 3.
0: Counter/Timer 3 uses the system clock divided by 12.
1: Counter/Timer 3 uses the system clock.
UNUSED. Read = 0, Write = don’t care.
TF3: Timer3 Overflow Flag.
(from SMBus)
SCL
R/W
Bit6
-
12
Crossbar
TOE
Figure 19.20. TMR3CN: Timer 3 Control Register
0
1
TR3
R/W
Bit5
-
Figure 19.19. Timer 3 Block Diagram
T3M
R/W
Bit4
-
Reload
TCLK
Rev. 1.7
R/W
Bit3
TMR3RLL TMR3RLH
-
TMR3L
TMR3H
TR3
R/W
Bit2
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
T3M
R/W
Bit1
T3M
TF3
TR3
(to ADC)
R/W
Bit0
-
Interrupt
SFR Address:
Reset Value
00000000
0x91
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