C8051F005DK Silicon Laboratories Inc, C8051F005DK Datasheet - Page 88

DEV KIT FOR F005/006/007

C8051F005DK

Manufacturer Part Number
C8051F005DK
Description
DEV KIT FOR F005/006/007
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet

Specifications of C8051F005DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F01x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F005
Silicon Family Name
C8051F00x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F005/006/007
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1188

Available stocks

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Manufacturer
Quantity
Price
Part Number:
C8051F005DK
Manufacturer:
SiliconL
Quantity:
1
11.2.
The Flash memory can be used for non-volatile data storage as well as program code. This allows data such as
calibration coefficients to be calculated and stored at run time. Data is written using the MOVX instruction and
read using the MOVC instruction.
The MCU incorporates an additional 128-byte sector of Flash memory located at 0x8000 – 0x807F. This sector can
be used for program code or data storage. However, its smaller sector size makes it particularly well suited as
general purpose, non-volatile scratchpad memory. Even though Flash memory can be written a single byte at a
time, an entire sector must be erased first. In order to change a single byte of a multi-byte data set, the data must be
moved to temporary storage. Next, the sector is erased, the data set updated and the data set returned to the original
sector. The 128-byte sector-size facilitates updating data without wasting program memory space by allowing the
use of internal data RAM for temporary storage. (A normal 512-byte sector is too large to be stored in the 256-byte
internal data memory.)
11.3.
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by software as
well as prevent the viewing of proprietary program code and constants.
(PSCTL.0) and the Program Store Erase Enable (PSCTL.1) bits protect the Flash memory from accidental
modification by software. These bits must be explicitly set to logic 1 before software can modify the Flash memory.
Additional security features prevent proprietary program code and data constants from being read or altered across
the JTAG interface or by software running on the system controller.
A set of security lock bytes stored at 0x7DFE and 0x7DFF protect the Flash program memory from being read or
altered across the JTAG interface. Each bit in a security lock-byte protects one 4kbyte block of memory. Clearing
a bit to logic 0 in a Read lock byte prevents the corresponding block of Flash memory from being read across the
JTAG interface. Clearing a bit in the Write/Erase lock byte protects the block from JTAG erasures and/or writes.
The Read lock byte is at location 0x7DFF. The Write/Erase lock byte is located at 0x7DFE. Figure 11.2 shows the
location and bit definitions of the security bytes. The 512-byte sector containing the lock bytes can be written to,
but not erased by software. Writing to the reserved area should not be performed.
Bits7-2: UNUSED. Read = 000000b, Write = don’t care.
Bit1:
Bit0:
R/W
Bit7
-
Non-volatile Data Storage
Security Options
Setting this bit allows an entire page of the Flash program memory to be erased provided
the PSWE bit is also set. After setting this bit, a write to Flash memory using the MOVX
instruction will erase the entire page that contains the location addressed by the MOVX
instruction. The value of the data byte written does not matter.
0: Flash program memory erasure disabled.
1: Flash program memory erasure enabled.
Setting this bit allows writing a byte of data to the Flash program memory using the
MOVX instruction. The location must be erased before writing data.
0: Write to Flash program memory disabled.
1: Write to Flash program memory enabled.
PSEE: Program Store Erase Enable.
PSWE: Program Store Write Enable.
R/W
Bit6
-
Figure 11.1. PSCTL: Program Store RW Control
R/W
Bit5
-
R/W
Bit4
-
Rev. 1.7
R/W
Bit3
-
R/W
Bit2
-
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
The Program Store Write Enable
PSEE
R/W
Bit1
PSWE
R/W
Bit0
SFR Address:
Reset Value
00000000
0x8F
88

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