US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 108

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 3 Exception Handling
Bits 1 and 0—IRQ
Bit n
IRRIn
0
1
Interrupt Request Register 2 (IRR2)
IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct
transfer, A/D converter, Timer G, Timer FH, Timer FL, Timer C, or asynchronous event counter
interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is
necessary to write 0 to clear each flag.
Bit 7—Direct Transfer Interrupt Request Flag (IRRDT)
Bit 7
IRRDT
0
1
Rev. 8.00 Mar. 09, 2010 Page 86 of 658
REJ09B0042-0800
Bit
Initial value
Read/Write
Note: * Only a write of 0 for flag clearing is possible
Description
Clearing condition:
When IRRIn = 1, it is cleared by writing 0
Setting condition:
When pin IRQn is designated for interrupt input and the designated signal edge is
input
Description
Clearing condition:
When IRRDT = 1, it is cleared by writing 0
Setting condition:
When a direct transfer is made by executing a SLEEP instruction while DTON = 1 in
SYSCR2
R/(W) *
IRRDT
1
7
0
and IRQ
IRRAD
R/(W) *
0
6
0
Interrupt Request Flags (IRRI1 and IRRI0)
⎯
⎯
W
5
IRRTG
R/(W) *
4
0
IRRTFH
R/(W) *
3
0
IRRTFL
R/(W) *
2
0
IRRTC
R/(W) *
1
0
(initial value)
(initial value)
(n = 1 or 0)
IRREC
R/(W) *
0
0