US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 47

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2.1
The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit
registers. Its concise instruction set is designed for high-speed operation.
2.1.1
Features of the H8/300L CPU are listed below.
• General-register architecture
• Instruction set with 55 basic instructions, including:
• Eight addressing modes
• 64-Kbyte address space
• High-speed operation
• Low-power operation modes
Note: * These values are at φ = 8 MHz.
Sixteen 8-bit general registers, also usable as eight 16-bit general registers
⎯ Multiply and divide instructions
⎯ Powerful bit-manipulation instructions
⎯ Register direct
⎯ Register indirect
⎯ Register indirect with displacement
⎯ Register indirect with post-increment or pre-decrement
⎯ Absolute address
⎯ Immediate
⎯ Program-counter relative
⎯ Memory indirect
⎯ All frequently used instructions are executed in two to four states
⎯ High-speed arithmetic and logic operations
⎯ 8- or 16-bit register-register add or subtract: 0.25 µs *
⎯ 8 × 8-bit multiply:
⎯ 16 ÷ 8-bit divide:
SLEEP instruction for transfer to low-power operation
Overview
Features
Section 2 CPU
1.75 µs *
1.75 µs *
Rev. 8.00 Mar. 09, 2010 Page 25 of 658
REJ09B0042-0800
Section 2 CPU