US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 91

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Example 2: BSET instruction executed designating port 3
P3
signal at P3
example, the BSET instruction is used to change pin P3
[A: Prior to executing BSET]
Input/output Input
Pin state
PCR3
PDR3
[B: BSET instruction executed]
[C: After executing BSET]
Input/output Input
Pin state
PCR3
PDR3
[D: Explanation of how BSET operates]
When the BSET instruction is executed, first the CPU reads port 3.
Since P3
P3
of H'80, but the value read by the CPU is H'40.
Next, the CPU sets bit 0 of the read data to 1, changing the PDR3 data to H'41. Finally, the CPU
writes this value (H'41) to PDR3, completing execution of BSET.
As a result of this operation, bit 0 in PDR3 becomes 1, and P3
However, bits 7 and 6 of PDR3 end up with different values.
BSET
7
5
and P3
to P3
7
0
and P3
are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a value
6
6
#0
are designated as input pins, with a low-level signal input at P3
. The remaining pins, P3
P3
Low level High level Low level Low level Low level Low level Low level Low level
0
1
P3
Low level High level Low level Low level Low level Low level Low level High level
0
0
7
7
6
,
are input pins, the CPU reads the pin states (low-level and high-level input).
@PDR3
P3
Input
0
0
P3
Input
0
1
6
6
P3
Output
P3
Output
0
1
0
1
The BSET instruction is executed designating port 3.
5
5
5
to P3
1
, are output pins and output low-level signals. In this
P3
Output
1
0
P3
Output
1
0
4
4
0
P3
Output
1
0
P3
Output
1
0
to high-level output.
Rev. 8.00 Mar. 09, 2010 Page 69 of 658
3
3
0
outputs a high-level signal.
P3
Output
1
0
P3
Output
1
0
2
2
7
and a high-level
P3
Output
1
0
P3
Output
1
0
REJ09B0042-0800
1
1
Section 2 CPU
P3
Output
1
0
P3
Output
1
1
0
0