US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 11

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 1 Overview................................................................................................1
1.1
1.2
1.3
Section 2 CPU......................................................................................................25
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Overview................................................................................................................................ 1
Internal Block Diagram.......................................................................................................... 7
Pin Arrangement and Functions............................................................................................. 9
1.3.1
1.3.2
Overview.............................................................................................................................. 25
2.1.1
2.1.2
2.1.3
Register Descriptions ........................................................................................................... 27
2.2.1
2.2.2
2.2.3
Data Formats ........................................................................................................................ 29
2.3.1
2.3.2
Addressing Modes................................................................................................................ 32
2.4.1
2.4.2
Instruction Set ...................................................................................................................... 38
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
2.5.7
2.5.8
Basic Operational Timing .................................................................................................... 55
2.6.1
2.6.2
CPU States ........................................................................................................................... 57
2.7.1
2.7.2
Pin Arrangement ....................................................................................................... 9
Pin Functions .......................................................................................................... 19
Features................................................................................................................... 25
Address Space......................................................................................................... 26
Register Configuration............................................................................................ 26
General Registers .................................................................................................... 27
Control Registers .................................................................................................... 27
Initial Register Values............................................................................................. 29
Data Formats in General Registers ......................................................................... 30
Memory Data Formats ............................................................................................ 31
Addressing Modes .................................................................................................. 32
Effective Address Calculation ................................................................................ 34
Data Transfer Instructions....................................................................................... 40
Arithmetic Operations............................................................................................. 42
Logic Operations..................................................................................................... 43
Shift Operations ...................................................................................................... 44
Bit Manipulations.................................................................................................... 46
Branching Instructions ............................................................................................ 50
System Control Instructions.................................................................................... 52
Block Data Transfer Instruction.............................................................................. 53
Access to On-Chip Memory (RAM, ROM)............................................................ 55
Access to On-Chip Peripheral Modules .................................................................. 56
Overview................................................................................................................. 57
Program Execution State......................................................................................... 59
Contents
Rev. 8.00 Mar. 09, 2010 Page ix of xx
REJ09B0042-0800