US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 187

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit 7—Power-down Disable (PDWND)
This bit selects the power-down mode of the flash memory when a transition to the subactive
mode is made.
Bit 7
PDWND
0
1
Bits 6 to 0—Reserved
These bits are always read as 0 and cannot be modified.
6.6.5
FENR controls CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR, and
FLPWCR.
Bit 7—Flash Memory Control Register Enable (FLSHE)
This bit controls access to the flash memory control registers.
Bit 7
FLSHE
0
1
Bits 6 to 0—Reserved
These bits are always read as 0 and cannot be modified.
Bit
Initial value
Read/Write
Flash Memory Enable Register (FENR)
Description
When this bit is 0 and a transition is made to the subactive mode, the flash memory
enters the power-down mode.
When this bit is 1, the flash memory remains in the normal mode even after a
transition is made to the subactive mode.
Description
Flash memory control registers cannot be accessed
Flash memory control registers can be accessed
FLSHE
R/W
7
0
—
—
6
0
—
—
5
0
—
—
4
0
Rev. 8.00 Mar. 09, 2010 Page 165 of 658
—
—
3
0
—
—
2
0
REJ09B0042-0800
—
—
Section 6 ROM
1
0
(initial value)
(initial value)
—
—
0
0