US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 600

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Appendix B Internal I/O Registers
TMG—Timer Mode Register G
Rev. 8.00 Mar. 09, 2010 Page 578 of 658
REJ09B0042-0800
Bit
Initial value
Read/Write
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
Timer Overflow Flag H
0 Clearing condition:
1 Setting condition:
After reading OVFH = 1, cleared by writing 0 to OVFH
Set when TCG overflows from H'FF to H'00
R/(W) *
OVFH
7
0
Timer Overflow Flag L
0 Clearing condition:
1 Setting condition:
After reading OVFL = 1, cleared by writing 0 to OVFL
Set when TCG overflows from H'FF to H'00
R/(W) *
OVFL
6
0
Timer Overflow Interrupt Enable
0 TCG overflow interrupt request is disabled
1 TCG overflow interrupt request is enabled
OVIE
R/W
5
0
Input Capture Interrupt Edge Select
0 Interrupt generated on rising edge of input capture
1 Interrupt generated on falling edge of input capture
input signal
input signal
IIEGS
Counter Clear
R/W
0
1 0 TCG cleared by rising edge of input capture
4
0
0
1 TCG cleared by falling edge of input capture
1 TCG cleared by both edges of input capture
TCG clearing is disabled
input signal
input signal
input signal
CCLR1
R/W
3
0
Clock Select
0
1 0 Internal clock: counting on φ/2
0
1 Internal clock: counting on φ/32
1 Internal clock: counting on φ
H'BC
CCLR0
Internal clock: counting on φ/64
R/W
2
0
CKS1
R/W
1
0
CKS0
R/W
0
0
Timer G
W
/4