US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 343

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Event Counter Control/Status Register (ECCSR)
ECCSR is an 8-bit read/write register that controls counter overflow detection, counter resetting,
and halting of the count-up function.
ECCSR is initialized to H'00 upon reset.
Bit 7—Counter Overflow H (OVH)
Bit 7 is a status flag indicating that ECH has overflowed from H'FF to H'00. This flag is set when
ECH overflows. It is cleared by software but cannot be set by software. OVH is cleared by
reading it when set to 1, then writing 0.
When ECH and ECL are used as a 16-bit event counter with CH2 cleared to 0, OVH functions as a
status flag indicating that the 16-bit event counter has overflowed from H'FFFF to H'0000.
Bit 7
OVH
0
1
Bit 6—Counter Overflow L (OVL)
Bit 6 is a status flag indicating that ECL has overflowed from H'FF to H'00. This flag is set when
ECL overflows. It is cleared by software but cannot be set by software. OVL is cleared by
reading it when set to 1, then writing 0.
Bit
Initial Value
Read/Write
Note:
*
Bits 7 and 6 can only be written with 0, for flag clearing.
Description
ECH has not overflowed
Clearing condition:
After reading OVH = 1, cleared by writing 0 to OVH
ECH has overflowed
Setting condition:
Set when ECH overflows from H’FF to H’00
R/W *
OVH
0
7
R/W *
OVL
0
6
R/W
⎯
0
5
CH2
R/W
4
0
Rev. 8.00 Mar. 09, 2010 Page 321 of 658
CUEH
R/W
0
3
CUEL
R/W
2
0
REJ09B0042-0800
CRCH
Section 9 Timers
R/W
0
1
(initial value)
CRCL
R/W
0
0