US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 54

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 2 CPU
2.4
2.4.1
The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a
subset of these addressing modes.
Table 2.1
Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general register
containing the operand.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general register
containing the address of the operand in memory.
Register Indirect with Displacement—@(d:16, Rn): The instruction has a second word (bytes 3
and 4) containing a displacement which is added to the contents of the specified general register to
obtain the operand address in memory.
This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address
must be even.
Rev. 8.00 Mar. 09, 2010 Page 32 of 658
REJ09B0042-0800
No.
1
2
3
4
5
6
7
8
Addressing Modes
Addressing Modes
Addressing Modes
Address Modes
Register direct
Register indirect
Register indirect with displacement
Register indirect with post-increment
Register indirect with pre-decrement
Absolute address
Immediate
Program-counter relative
Memory indirect
Symbol
Rn
@Rn
@(d:16, Rn)
@Rn+
@–Rn
@aa:8 or @aa:16
#xx:8 or #xx:16
@(d:8, PC)
@@aa:8