US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 151

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.2.2
Sleep mode is cleared by any interrupt (timer A, timer C, timer F, timer G, asynchronous event
counter, IRQAEC, IRQ
the RES pin.
• Clearing by interrupt
•
5.2.3
Operation in sleep (medium-speed) mode is clocked at the frequency designated by the MA1 and
MA0 bits in SYSCR1.
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts.
A transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep
(medium-speed) mode to active (medium-speed) mode. Sleep mode is not cleared if the I bit of
the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the
interrupt enable register.
To synchronize the interrupt request signal with the system clock, up to 2/φ(s) delay may occur
after the interrupt request signal occurrence, before the interrupt exception handling start.
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.
Clearing by RES input
Clearing Sleep Mode
Clock Frequency in Sleep (Medium-Speed) Mode
4
, IRQ
3
, IRQ
1
, IRQ
0
, WKP
7
to WKP
Rev. 8.00 Mar. 09, 2010 Page 129 of 658
0
, SCI3, A/D converter), or by input at
Section 5 Power-Down Modes
REJ09B0042-0800