AN2131-DK001 Cypress Semiconductor Corp, AN2131-DK001 Datasheet - Page 123

• Manufacturer Part Number: AN2131-DK001
• Description: KIT EZ-USB DEVELOPMENT BOARD
• Manufacturer: Cypress Semiconductor Corp

Specifications of AN2131-DK001

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1333

Endpoint zero accepts a special SETUP packet, which contains an 8-byte data structure
that provides host information about the CONTROL transaction. CONTROL transfers
include a final STATUS phase, constructed from standard PIDs (IN/OUT, DATA1, and
ACK/NAK).
Some CONTROL transactions include all required data in their 8-byte SETUP Data
packet. Other CONTROL transactions require more OUT data than will fit into the eight
bytes, or require IN data from the device. These transactions use standard bulk-like trans-
fers to move the data. Note in Figure 7-1 that the “DATA Stage” looks exactly like a bulk
transfer. As with BULK endpoints, the endpoint zero byte count registers must be loaded
to ACK the data transfer stage of a CONTROL transfer.
Page 7-2
7.2
Token Packet
Token Packet
Token Packet
S
E
T
U
P
N
I
O
U
T
Control Endpoint EP0
A
D
D
R
A
D
D
R
A
D
D
R
E
N
D
P
E
N
D
P
E
N
D
P
SUTOK Interrupt
Core sets HSNAK=1
C
R
C
5
C
R
C
5
C
R
C
5
SETUP Stage
Figure 7-1. A USB Control Transfer (This One Has a Data Stage)
Data Pkt
D
A
T
A
1
D
A
T
A
1
D
A
T
A
0
Data Packet
Data Packet
C
R
C
1
6
8 bytes
Setup
Data
Payload
Data
H/S Pkt
S
Y
N
C
N
A
K
STATUS Stage
C
R
C
1
6
....
C
R
C
1
6
H/S Pkt
Chapter 7. EZ-USB CPU
H/S Pkt
A
C
K
DATA Stage
SUDAV Interrupt
A
C
K
8051 clears HSNAK bit (writes 1 to it)
or sets the STALL bit.
EP0-IN Interrupt
Token Packet
O
U
T
Token Packet
N
I
A
D
D
R
A
D
D
R
E
N
D
P
E
N
D
P
C
R
C
5
C
R
C
5
Data Pkt
D
A
T
A
1
D
A
T
A
0
C
R
C
1
6
Data Packet
EP0-IN Interrupt
Payload
H/S Pkt
Data
A
C
K
C
R
C
1
6
EZ-USB TRM v1.9
H/S Pkt
A
C
K