AN2131-DK001 Cypress Semiconductor Corp, AN2131-DK001 Datasheet - Page 67

• Manufacturer Part Number: AN2131-DK001
• Description: KIT EZ-USB DEVELOPMENT BOARD
• Manufacturer: Cypress Semiconductor Corp

Specifications of AN2131-DK001

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1333

4.4
The USB core contains an I
interface. This controller uses the SCL (Serial Clock) and SDA (Serial Data) pins. I2C
Controller describes how the boot load operates at power-on to read the contents of an
external serial EEPROM to determine the initial EZ-USB FX configuration. The boot
loader operates automatically, while the 8051 is held in reset. The last section of this chap-
ter describes the operating details of the boot loader.
After the boot sequence completes and the 8051 is brought out of reset, the general-pur-
pose I
other EEPROMS, I/O chips, audio/video control chips, etc.
4.5
Figure 4-5 illustrates the waveforms for an I
USB pins, which must be pulled up to Vcc with external resistors. The EZ-USB chip is an
I
pulses on SCL by driving low. Once the master drives SCL low, external slave devices can
also drive SCL low to extend clock cycle times.
To synchronize I
low, and must be valid while SCL is high. Two exceptions to this rule are used to generate
START and STOP conditions. A START condition is defined as SDA going low, while
SCL is high, and a STOP condition is defined as SDA going high, while SCL is high. Data
is sent MSB first. During the last bit time (clock #9 in Figure 4-5), the master (EZ-USB)
floats the SDA line to allow the slave to acknowledge the transfer by pulling SDA low.
Page 4-6
2
C bus master only, meaning that it synchronizes data transfers by generating clock
SDA
SCL
2
C controller is available to the 8051 for interface to external I
I
8051 I
2
C Controller
start
2
C Controller
2
C data, serial data (SDA) is permitted to change state only while SCL is
D7
1
2
D6
2
C controller for boot loading and general-purpose I
Figure 4-5. General I
D5
3
Chapter 4. EZ-USB CPU
D4
4
2
C transfer. SCL and SDA are open-drain EZ-
D3
5
2
C Transfer
D2
6
D1
7
D0
8
2
C devices, such as
ACK
9
EZ-USB TRM v1.9
2
C bus
stop