AN2131-DK001 Cypress Semiconductor Corp, AN2131-DK001 Datasheet - Page 74

KIT EZ-USB DEVELOPMENT BOARD

AN2131-DK001

Manufacturer Part Number
AN2131-DK001
Description
KIT EZ-USB DEVELOPMENT BOARD
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of AN2131-DK001

Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1333
The I
address or a two-byte-address EEPROM is attached. This test proceeds as follows:
EZ-USB TRM v1.9
1. The I
2. The I
3. The I
2
C controller performs a three-step test at power-on to determine whether a one-byte-
000 (10100001). If no ACK is returned, the controller proceeds to step 2. If ACK
is returned, the one-byte-address device is indicated. The controller discards the
data and proceeds to step 3.
001 (10100011). If ACK is returned, the two-byte-address device is indicated.
The controller discards the data and proceeds to step 3. If no ACK is returned, the
controller assumes that a valid EEPROM is not connected, assumes the “No Serial
EEPROM” mode, and terminates the boot load.
ate number of address bytes), then reads the first EEPROM byte. If it does not
read 0xB0 or 0xB2, the controller assumes the “No Serial EEPROM” mode. If it
reads either 0xB0 or 0xB2, the controller copies the next six bytes into internal
storage, and if it reads 0xB2, it proceeds to load the EEPROM contents into inter-
nal RAM.
2
2
2
C controller sends out a “read current address” command to I
C controller sends out a “read current address” command to I
C controller resets the EEPROM address pointer to zero (using the appropri-
Table 4-2. Strap Boot EEPROM Address Lines to These Values
* This EEPROM does not have address pins
Bytes
128
256
4K
8K
16
EEPROM
Example
24LC00*
24LC01
24LC02
24LC32
24LC64
Chapter 4. EZ-USB CPU
N/A
A2
0
0
0
0
N/A
A1
0
0
0
0
N/A
A0
0
0
1
1
2
2
C sub-address
C sub-address
Page 4-13

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