PIC12C672-10/SM Microchip Technology, PIC12C672-10/SM Datasheet - Page 106

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PIC12C672-10/SM

Manufacturer Part Number
PIC12C672-10/SM
Description
IC MCU OTP 2KX14 A/D 8-SOIJ
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets

Specifications of PIC12C672-10/SM

Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
For Use With
XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOICISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Other names
PIC12C672-10/SMR
PIC12C672-10/SMR
PICmicro MID-RANGE MCU FAMILY
6.3.4
DS31006A-page 6-12
Indirect Addressing, INDF, and FSR Registers
Indirect addressing is a mode of addressing data memory where the data memory address in
the instruction is not fixed. An SFR register is used as a pointer to the data memory location that
is to be read or written. Since this pointer is in RAM, the contents can be modified by the pro-
gram. This can be useful for data tables in the data memory.
indirect addressing. This shows the moving of the value to the data memory address specified
by the value of the FSR register.
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register
actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF reg-
ister itself indirectly (FSR = '0') will read 00h. Writing to the INDF register indirectly results in a
no-operation (although status bits may be affected). An effective 9-bit address is generated by
the concatenation of the IRP bit (STATUS<7>) with the 8-bit FSR register, as shown in
Figure 6-7: Indirect Addressing
Instruction
Executed
Instruction
Fetched
Opcode
Opcode
Address != 0
RP1:RP0
2
Address
File
9
7
9
Address = 0h
File Address = INDF
IRP
9
Figure 6-7
FSR
RAM
1997 Microchip Technology Inc.
shows the operation of
Figure
6-8.

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