PIC12C672-10/SM Microchip Technology, PIC12C672-10/SM Datasheet - Page 52

• Manufacturer Part Number: PIC12C672-10/SM
• Description: IC MCU OTP 2KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672-10/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOICISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Other names: PIC12C672-10/SMR; PIC12C672-10/SMR

PICmicro MID-RANGE MCU FAMILY
3.1
DS31003A-page 3-2
Introduction
The reset logic is used to place the device into a known state. The source of the reset can be
determined by using the device status bits. The reset logic is designed with features that reduce
system cost and increase system reliability.
Devices differentiate between various kinds of reset:
a)
b)
c)
d)
e)
f)
Most registers are unaffected by a reset; their status is unknown on POR and unchanged by all
other resets. The other registers are forced to a “reset state” on Power-on Reset, MCLR, WDT
reset, Brown-out Reset, Parity Error Reset, and on MCLR reset during SLEEP.
The on-chip parity bits that can be used to verify the contents of program memory.
Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of nor-
mal operation. Status bits TO, PD, POR, BOR, and PER are set or cleared differently in different
reset situations as indicated in
of the reset. See
A simplified block diagram of the on-chip reset circuit is shown in
is a superset of reset features. To determine the features that are available on a specific device,
please refer to the device’s Data Sheet.
All new devices will have a noise filter in the MCLR reset path to detect and ignore small pulses.
See
Note:
Power-on Reset (POR)
MCLR reset during normal operation
MCLR reset during SLEEP
WDT reset during normal operation
Brown-out Reset (BOR)
Parity Error Reset (PER)
parameter 30
While the PICmicro™ is in a reset state, the internal phase clock is held at Q1
(beginning of an instruction cycle).
Table 3-4
in the
“Electrical Specifications”
for a full description of the reset states of all registers.
Table
3-2. These bits are used in software to determine the nature
section for pulse width specification.
Figure
1997 Microchip Technology Inc.
3-1. This block diagram