PIC12C672-10/SM Microchip Technology, PIC12C672-10/SM Datasheet - Page 132

• Manufacturer Part Number: PIC12C672-10/SM
• Description: IC MCU OTP 2KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672-10/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOICISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Other names: PIC12C672-10/SMR; PIC12C672-10/SMR

PICmicro MID-RANGE MCU FAMILY
8.3
8.4
DS31008A-page 8-10
INSTRUCTION FLOW
Note 1: INTF flag is sampled here (every Q1).
GIE bit
(INTCON<7>)
INTF flag
(INTCON<1>)
CLKOUT
INT pin
OSC1
Instruction
executed
Instruction
fetched
PC
2: Interrupt latency = 3-4 T
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
Latency is the same whether Instruction (PC) is a single cycle or a 2-cycle instruction.
Interrupt Latency
INT and External Interrupts
3
Q1
Inst (PC-1)
Inst (PC)
Interrupt latency is defined as the time from the interrupt event (the interrupt flag bit gets set) to
the time that the instruction at address 0004h starts execution (when that interrupt is enabled).
For synchronous interrupts (typically internal), the latency is 3T
For asynchronous interrupts (typically external), such as the INT or Port RB Change Interrupt,
the interrupt latency will be 3 - 3.75T
when the interrupt event occurs
The latency is the same for both one and two cycle instructions.
The external interrupt on the INT pin is edge triggered: either rising if the INTEDG bit
(OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the INT
pin, the INTF flag bit (INTCON<1>) is set. This interrupt can be enabled/disabled by setting/clear-
ing the INTE enable bit (INTCON<4>). The INTF bit must be cleared in software in the interrupt
service routine before re-enabling this interrupt. The INT interrupt can wake-up the processor
from SLEEP, if the INTE bit was set prior to going into SLEEP. The status of the GIE bit decides
whether or not the processor branches to the interrupt vector following wake-up. See the
“Watchdog Timer and Sleep Mode”
from SLEEP through INT interrupt.
Figure 8-2: INT Pin and Other External Interrupt Timing
1
Q2
PC
Note:
Q3
4
CY
Q4
5
Any interrupts caused by external signals (such as timers, capture, change on port)
will have similar timing.
where T
Q1
Inst (PC+1)
Inst (PC)
CY
Q2
1
= instruction cycle time.
PC+1
Q3
Q4
(Figure
Interrupt Latency
Q1
Dummy Cycle
CY
section for details on SLEEP and for timing of wake-up
8-2) in relation to the instruction cycle.
Q2
PC+1
(instruction cycles). The exact latency depends upon
—
Q3
Q4
2
Q1
Dummy Cycle
Inst (0004h)
Q2
0004h
CY
Q3
.
1997 Microchip Technology Inc.
Q4
Q1
Inst (0005h)
Q2
Inst (0004h)
0005h
Q3
Q4