PIC12C672-10/SM Microchip Technology, PIC12C672-10/SM Datasheet - Page 678

• Manufacturer Part Number: PIC12C672-10/SM
• Description: IC MCU OTP 2KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672-10/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOICISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Other names: PIC12C672-10/SMR; PIC12C672-10/SMR

PICmicro MID-RANGE MCU FAMILY
I
DS31035A-page 35-6
I
Inter-Integrated Circuit. This is a two wire communication interface. This feature is one of the
modes of the SSP module.
Indirect Addressing
When the Data Memory Address is not contained in the Instruction. The instruction operates on
the INDF address, which causes the Data Memory Address to be the value in the FSR register.
The execution of the instruction will always access the data at the address pointed to by the FSR
register.
Instruction Bus
The bus which is used to transfer instruction words from the program memory to the CPU.
Instruction Fetch
Due to the Harvard architecture, when one instruction is to be executed, the next location in pro-
gram memory is “fetched” and ready to be decoded as soon as the currently executing instruction
is completed.
Instruction cycle
The events for an instruction to execute. There are four events which can generally be described
as: Decode, Read, Execute, and Write. Not all events will be done by all instructions. To see the
operations during the instruction cycle, please look in the description of each instruction. Four
external clocks (Tosc) make one instruction cycle (T
Interrupt
A signal to the CPU that causes the program flow to be forced to the Interrupt Vector Address
(04h in program memory). Before the program flow is changed, the contents of the Program
Counter (PC) are forced onto the hardware stack, so that program execution may return to the
interrupted point.
INTRC
Internal Resistor-Capacitor (RC). Some devices have a device oscillator option that allows the
clock to come from an internal RC.
2
C
CY
).
1997 Microchip Technology Inc.