PIC12C672-10/SM Microchip Technology, PIC12C672-10/SM Datasheet - Page 147

• Manufacturer Part Number: PIC12C672-10/SM
• Description: IC MCU OTP 2KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672-10/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOICISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Other names: PIC12C672-10/SMR; PIC12C672-10/SMR

1997 Microchip Technology Inc.
Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded
from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the
old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed
together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can
clear the interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch
condition, and allow flag bit RBIF to be cleared.
This interrupt on mismatch feature, together with software configurable pull-ups on these four
pins allow easy interface to a keypad and make it possible for wake-up on key-depression.
The interrupt on change feature is recommended for wake-up on key depression and operations
where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recom-
mended while using the interrupt on change feature.
Figure 9-5: Block Diagram of RB7:RB4 Pins
Any read or write of PORTB. This will end the mismatch condition.
Clear flag bit RBIF.
Note 1: I/O pins have diode protection to V
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
3: In sleep mode the device is in Q1 state.
RB7:RB6 in serial programming mode
Data bus
WR TRIS
WR Port
RBPU
and clear the RBPU bit (OPTION<7>).
Set RBIF
From other
RB7:RB4 pins
(2)
RD TRIS
RD Port
Data Latch
TRIS Latch
D
D
CK
CK
Section 9. I/O Ports
Q
Q
DD
Q
Q
Latch
and V
EN
EN
D
D
TTL
Input
Buffer
SS
.
V
P
DD
weak
pull-up
RD Port
Buffer
I/O
pin
Q1
DS31009A-page 9-7
Q3
(1)
ST
9