DSPIC30F3013-30I/SO Microchip Technology, DSPIC30F3013-30I/SO Datasheet - Page 108

• Manufacturer Part Number: DSPIC30F3013-30I/SO
• Description: IC DSPIC MCU/DSP 24K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3013-30I/SO

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301330ISO

dsPIC30F
If the value in a particular duty cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the duty cycle register is equal to
the value held in the PTPER register.
FIGURE 15-4:
15.5
There are four 16-bit special function registers (PDC1,
PDC2, PDC3 and PDC4) used to specify duty cycle
values for the PWM module.
The value in each duty cycle register determines the
amount of time that the PWM output is in the active
state. The duty cycle registers are 16-bits wide. The LS
bit of a duty cycle register determines whether the
PWM edge occurs in the beginning. Thus, the PWM
resolution is effectively doubled.
15.5.1
The four PWM duty cycle registers are double buffered
to allow glitchless updates of the PWM outputs. For
each duty cycle, there is a duty cycle register that is
accessible by the user and a second duty cycle register
that holds the actual compare value used in the present
PWM period.
For edge aligned PWM output, a new duty cycle value
will be updated whenever a match with the PTPER reg-
ister occurs and PTMR is reset. The contents of the
duty cycle buffers are automatically loaded into the
duty cycle registers when the PWM time base is dis-
abled (PTEN = 0) and the UDIS bit is cleared in
PWMCON2.
When the PWM time base is in the Up/Down Counting
mode, new duty cycle values are updated when the
value of the PTMR register is zero and the PWM time
base begins to count upwards. The contents of the duty
cycle buffers are automatically loaded into the duty
cycle registers when the PWM time base is disabled
(PTEN = 0).
DS70082G-page 106
PTPER
Duty
Cycle
0
PWM Duty Cycle Comparison
Units
DUTY CYCLE REGISTER BUFFERS
Period/2
CENTER ALIGNED PWM
Period
PTMR
Value
Preliminary
When the PWM time base is in the Up/Down Counting
mode with double updates, new duty cycle values are
updated when the value of the PTMR register is zero,
and when the value of the PTMR register matches the
value in the PTPER register. The contents of the duty
cycle buffers are automatically loaded into the duty
cycle registers when the PWM time base is disabled
(PTEN = 0).
15.6
In the Complementary mode of operation, each pair of
PWM outputs is obtained by a complementary PWM
signal. A dead-time may be optionally inserted during
device switching, when both outputs are inactive for a
short period (Refer to Section 15.7).
In Complementary mode, the duty cycle comparison
units are assigned to the PWM outputs as follows:
• PDC1 register controls PWM1H/PWM1L outputs
• PDC2 register controls PWM2H/PWM2L outputs
• PDC3 register controls PWM3H/PWM3L outputs
• PDC4 register controls PWM4H/PWM4L outputs
The Complementary mode is selected for each PWM
I/O pin pair by clearing the appropriate PMODx bit in the
PWMCON1 SFR. The PWM I/O pins are set to
Complementary mode by default upon a device Reset.
15.7
Dead-time generation may be provided when any of
the PWM I/O pin pairs are operating in the Comple-
mentary Output mode. The PWM outputs use Push-
Pull drive circuits. Due to the inability of the power out-
put devices to switch instantaneously, some amount of
time must be provided between the turn off event of one
PWM output in a complementary pair and the turn on
event of the other transistor.
The PWM module allows two different dead-times to be
programmed. These two dead-times may be used in
one of two methods described below to increase user
flexibility:
• The PWM output signals can be optimized for dif-
• The two dead-times can be assigned to individual
ferent turn off times in the high side and low side
transistors in a complementary pair of transistors.
The first dead-time is inserted between the turn
off event of the lower transistor of the complemen-
tary pair and the turn on event of the upper tran-
sistor. The second dead-time is inserted between
the turn off event of the upper transistor and the
turn on event of the lower transistor.
PWM I/O pin pairs. This Operating mode allows
the PWM module to drive different transistor/load
combinations with each complementary PWM I/O
pin pair.
Complementary PWM Operation
Dead-Time Generators
 2004 Microchip Technology Inc.