DSPIC30F3013-30I/SO Microchip Technology, DSPIC30F3013-30I/SO Datasheet - Page 38

• Manufacturer Part Number: DSPIC30F3013-30I/SO
• Description: IC DSPIC MCU/DSP 24K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3013-30I/SO

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301330ISO

dsPIC30F
TABLE 3-2:
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes or 32K words.
3.2.2
The core data width is 16-bits. All internal registers are
organized as 16-bit wide words. Data space memory is
organized in byte addressable, 16-bit wide blocks.
3.2.3
To
PICmicro
usage efficiency, the dsPIC30F instruction set supports
both word and byte operations. Data is aligned in data
memory and registers as words, but all data space EAs
resolve to bytes. Data byte reads will read the complete
word, which contains the byte, using the LS bit of any
EA to determine which byte to select. The selected byte
is placed onto the LS Byte of the X data path (no byte
accesses are possible from the Y data path as the MAC
class of instruction can only fetch words). That is, data
memory and registers are organized as two parallel
byte wide entities with shared (word) address decode,
but separate write lines. Data byte writes only write to
the corresponding side of the array or register which
matches the byte address.
As a consequence of this byte accessibility, all effective
address calculations (including those generated by the
DSP operations, which are restricted to word sized
data) are internally scaled to step through word aligned
memory. For example, the core would recognize that
Post-Modified Register Indirect Addressing mode,
[Ws++], will result in a value of Ws+1 for byte opera-
tions and Ws+2 for word operations.
All word accesses must be aligned to an even address.
Mis-aligned word data fetches are not supported, so
care must be taken when mixing byte and word opera-
tions, or translating from 8-bit MCU code. Should a mis-
aligned read or write be attempted, an Address Error
trap will be generated. If the error occurred on a read,
the instruction underway is completed, whereas if it
occurred on a write, the instruction will be executed but
the write will not occur. In either case, a trap will then
be executed, allowing the system and/or user to exam-
ine the machine state prior to execution of the address
fault.
DS70082G-page 36
Attempted Operation
EA = an unimplemented address
W8 or W9 used to access Y data
space in a MAC instruction
W10 or W11 used to access X
data space in a MAC instruction
help
®
devices and improve data space memory
DATA SPACE WIDTH
DATA ALIGNMENT
maintain
EFFECT OF INVALID
MEMORY ACCESSES
backward
compatibility
Data Returned
0x0000
0x0000
0x0000
with
Preliminary
FIGURE 3-6:
All byte loads into any W register are loaded into the LS
Byte. The MSB is not modified.
A sign-extend (SE) instruction is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
zero-extend (ZE) instruction on the appropriate
address.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions, including the DSP instructions, operate
only on words.
3.2.4
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent linear
addressing space, X and Y spaces have contiguous
addresses.
When executing any instruction other than one of the
MAC class of instructions, the X block consists of the 64
Kbyte data address space (including all Y addresses).
When executing one of the MAC class of instructions,
the X block consists of the 64 Kbyte data address
space excluding the Y address block (for data reads
only). In other words, all other instructions regard the
entire data memory as one composite address space.
The MAC class instructions extract the Y address space
from data space and address it using EAs sourced from
W10 and W11. The remaining X data space is
addressed using W8 and W9. Both address spaces are
concurrently accessed only with the MAC class
instructions.
An example data space memory map is shown in
Figure 3-8.
0001
0003
0005
15
DATA SPACE MEMORY MAP
MS Byte
Byte 1
Byte 3
Byte 5
DATA ALIGNMENT
 2004 Microchip Technology Inc.
8 7
LS Byte
Byte 0
Byte 2
Byte 4
0
0000
0002
0004