DSPIC30F3013-30I/SO Microchip Technology, DSPIC30F3013-30I/SO Datasheet - Page 240

• Manufacturer Part Number: DSPIC30F3013-30I/SO
• Description: IC DSPIC MCU/DSP 24K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3013-30I/SO

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301330ISO

dsPIC30F
Timing Specifications
U
UART
DS70082G-page 238
Type C Timer External Clock .................................... 199
Watchdog Timer........................................................ 197
PLL Clock.................................................................. 194
Address Detect Mode ............................................... 127
Auto Baud Support.................................................... 128
Baud Rate Generator ................................................ 127
Enabling and Setting Up UART ................................ 125
Loopback Mode ........................................................ 127
Module Overview ...................................................... 123
Operation During CPU Sleep and Idle Modes .......... 128
Receiving Data.......................................................... 126
Alternate I/O...................................................... 125
Disabling ........................................................... 125
Enabling ............................................................ 125
Setting Up Data, Parity and Stop Bit
In 8-bit or 9-bit Data Mode ................................ 126
Interrupt............................................................. 126
Receive Buffer (UxRCB) ................................... 126
Selections ................................................. 125
Preliminary
Unit ID Locations .............................................................. 151
Universal Asynchronous Receiver Transmitter. See UART.
W
Wake-up from Sleep ......................................................... 151
Wake-up from Sleep and Idle ............................................. 55
Watchdog Timer
Watchdog Timer (WDT)............................................ 151, 161
WWW, On-Line Support ..................................................... 12
Reception Error Handling ......................................... 126
Transmitting Data ..................................................... 125
UART1 Register Map................................................ 129
UART2 Register Map................................................ 129
Timing Characteristics .............................................. 196
Timing Requirements................................................ 197
Enabling and Disabling ............................................. 161
Operation .................................................................. 161
Framing Error (FERR) ...................................... 127
Idle Status......................................................... 127
Parity Error (PERR) .......................................... 127
Receive Break .................................................. 127
Receive Buffer Overrun Error (OERR Bit) ........ 126
In 8-bit Data Mode ............................................ 125
In 9-bit Data Mode ............................................ 125
Interrupt ............................................................ 126
Transmit Buffer (UxTXB) .................................. 125
 2004 Microchip Technology Inc.