DSPIC30F3013-30I/SO Microchip Technology, DSPIC30F3013-30I/SO Datasheet - Page 115

• Manufacturer Part Number: DSPIC30F3013-30I/SO
• Description: IC DSPIC MCU/DSP 24K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3013-30I/SO

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301330ISO

16.2
The module supports a basic framed SPI protocol in
Master or Slave mode. The control bit FRMEN enables
framed SPI support and causes the SSx pin to perform
the frame synchronization pulse (FSYNC) function.
The control bit SPIFSD determines whether the SSx
pin is an input or an output (i.e., whether the module
receives or generates the frame synchronization
pulse). The frame pulse is an active high pulse for a sin-
gle SPI clock cycle. When frame synchronization is
enabled, the data transmission starts only on the sub-
sequent transmit edge of the SPI clock.
16.3
The SSx pin allows a Synchronous Slave mode. The
SPI must be configured in SPI Slave mode, with SSx
pin control enabled (SSEN = 1). When the SSx pin is
low, transmission and reception are enabled, and the
SDOx pin is driven. When SSx pin goes high, the SDOx
pin is no longer driven. Also, the SPI module is re-
synchronized, and all counters/control circuitry are
reset. Therefore, when the SSx pin is asserted low
again, transmission/reception will begin at the MS bit,
even if SSx had been de-asserted in the middle of a
transmit/receive.
 2004 Microchip Technology Inc.
Framed SPI Support
Slave Select Synchronization
Preliminary
16.4
During Sleep mode, the SPI module is shut-down. If
the CPU enters Sleep mode while an SPI transaction
is in progress, then the transmission and reception is
aborted.
The transmitter and receiver will stop in Sleep mode.
However, register contents are not affected by
entering or exiting Sleep mode.
16.5
When the device enters Idle mode, all clock sources
remain functional. The SPISIDL bit (SPIxSTAT<13>)
selects if the SPI module will stop or continue on Idle.
If SPISIDL = 0, the module will continue to operate
when the CPU enters Idle mode. If SPISIDL = 1, the
module will stop when the CPU enters Idle mode.
SPI Operation During CPU Sleep
Mode
SPI Operation During CPU Idle
Mode
dsPIC30F
DS70082G-page 113