DSPIC30F3013-30I/SO Microchip Technology, DSPIC30F3013-30I/SO Datasheet - Page 22

• Manufacturer Part Number: DSPIC30F3013-30I/SO
• Description: IC DSPIC MCU/DSP 24K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3013-30I/SO

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301330ISO

dsPIC30F
2.2
The programmer’s model is shown in Figure 2-1 and
consists of 16x16-bit working registers (W0 through
W15), 2x40-bit accumulators (AccA and AccB),
STATUS register (SR), Data Table Page register
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART,
DOEND, DCOUNT and RCOUNT), and Program
Counter (PC). The working registers can act as data,
address or offset registers. All registers are memory
mapped. W0 acts as the W register for file register
addressing.
Some of these registers have a shadow register asso-
ciated with each of them, as shown in Figure 2-1. The
shadow register is used as a temporary holding register
and can transfer its contents to or from its host register
upon the occurrence of an event. None of the shadow
registers are accessible directly. The following rules
apply for transfer of registers into and out of shadows.
• PUSH.S and POP.S
• DO instruction
When a byte operation is performed on a working reg-
ister, only the Least Significant Byte of the target regis-
ter is affected. However, a benefit of memory mapped
working registers is that both the Least and Most Sig-
nificant Bytes can be manipulated through byte wide
data memory space accesses.
2.2.1
The dsPIC
the dedicated software stack pointer (SP), and will be
automatically modified by exception processing and
subroutine calls and returns. However, W15 can be ref-
erenced by any instruction in the same manner as all
other W registers. This simplifies the reading, writing
and manipulation of the stack pointer (e.g., creating
stack frames).
W15 is initialized to 0x0800 during a Reset. The user
may reprogram the SP during initialization to any
location within data space.
W14 has been dedicated as a stack frame pointer as
defined by the LNK and ULNK instructions. However,
W14 can be referenced by any instruction in the same
manner as all other W registers.
DS70082G-page 20
W0, W1, W2, W3, SR (DC, N, OV, Z and C bits
only) are transferred.
DOSTART, DOEND, DCOUNT shadows are
pushed on loop start, and popped on loop end.
Note:
Programmer’s Model
®
SOFTWARE STACK POINTER/
FRAME POINTER
In order to protect against misaligned
stack accesses, W15<0> is always clear.
devices contain a software stack. W15 is
Preliminary
2.2.2
The dsPIC core has a 16-bit status register (SR), the
LS Byte of which is referred to as the SR Low Byte
(SRL) and the MS Byte as the SR High Byte (SRH).
See Figure 2-1 for SR layout.
SRL contains all the MCU ALU operation status flags
(including the Z bit), as well as the CPU Interrupt Prior-
ity Level status bits, IPL<2:0>, and the REPEAT active
status bit, RA. During exception processing, SRL is
concatenated with the MS Byte of the PC to form a
complete word value which is then stacked.
The upper byte of the STATUS register contains the
DSP Adder/Subtractor status bits, the DO Loop Active
bit (DA) and the Digit Carry (DC) status bit.
Most SR bits are read/write. Exceptions are:
1.
2.
3.
4.
2.2.2.1
Instructions that use a carry/borrow input (ADDC,
CPB, SUBB and SUBBR) will only be able to clear Z
(for a non-zero result) and can never set it. A multi-
precision sequence of instructions, starting with an
instruction with no carry/borrow input, will thus auto-
matically logically AND the successive results of the
zero test. All results must be zero for the Z flag to
remain set by the end of the sequence.
All other instructions can set as well as clear the Z bit.
2.2.3
The Program Counter is 23 bits wide. Bit 0 is always
clear. Therefore, the PC can address up to 4M
instruction words.
Note 1: Clearing the SAB bit will also clear both
The DA bit: DA is read and clear only, because
accidentally setting it could cause erroneous
operation.
The RA bit: RA is a read only bit, because acci-
dentally setting it could cause erroneous opera-
tion. RA is only set on entry into a repeat loop,
and cannot be directly cleared by software.
The OV, OA, OB and OAB bits: These bits are
read only and can only be set by the DSP engine
overflow logic.
The SA, SB and SAB bits: These are read and
clear only and can only be set by the DSP
engine saturation logic. Once set, these flags
remain set until cleared by the user, irrespective
of the results from any subsequent DSP
operations.
2: When the memory mapped status regis-
STATUS REGISTER
PROGRAM COUNTER
the SA and SB bits.
ter (SR) is the destination address for an
operation which affects any of the SR bits,
data writes are disabled to all bits.
Z Status Bit
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