DSPIC30F3013-30I/SO Microchip Technology, DSPIC30F3013-30I/SO Datasheet - Page 56

• Manufacturer Part Number: DSPIC30F3013-30I/SO
• Description: IC DSPIC MCU/DSP 24K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3013-30I/SO

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301330ISO

dsPIC30F
5.
6.
• Stack Error Trap:
1.
2.
• Oscillator Fail Trap:
5.3.2
It is possible that multiple traps can become active
within the same cycle (e.g., a misaligned word stack
write to an overflowed address). In such a case, the
fixed priority shown in Figure 5-2 is implemented,
which may require the user to check if other traps are
pending, in order to completely correct the fault.
‘Soft’ traps include exceptions of priority level 8 through
level 11, inclusive. The arithmetic error trap (level 11)
falls into this category of traps. Soft traps can be treated
like non-maskable sources of interrupt that adhere to
the priority assigned by their position in the IVT. Soft
traps are processed like interrupts and require 2 cycles
to be sampled and acknowledged prior to exception
processing. Therefore, additional instructions may be
executed before a soft trap is acknowledged.
‘Hard’ traps include exceptions of priority level 12
through level 15, inclusive. The address error (level
12), stack error (level 13) and oscillator error (level 14)
traps fall into this category.
Like soft traps, hard traps can also be viewed as non-
maskable sources of interrupt. The difference between
hard traps and soft traps is that hard traps force the
CPU to stop code execution after the instruction caus-
ing the trap has completed. Normal program execution
flow will not resume until after the trap has been
acknowledged and processed.
If a higher priority trap occurs while any lower priority
trap is in progress, processing of the lower priority trap
will be suspended and the higher priority trap will be
acknowledged and processed. The lower priority trap
will remain pending until processing of the higher
priority trap completes.
DS70082G-page 54
This trap is initiated under the following
conditions:
This trap is initiated if the external oscillator fails
and operation becomes reliant on an internal RC
backup.
Execution of a “BRA #literal” instruction or a
“GOTO #literal” instruction, where literal
is an unimplemented program memory address.
Executing instructions after modifying the PC to
point to unimplemented program memory
addresses. The PC may be modified by loading
a value into the stack and executing a RETURN
instruction.
The stack pointer is loaded with a value which is
greater than the (user programmable) limit value
written into the SPLIM register (stack overflow).
The stack pointer is loaded with a value which is
less than 0x0800 (simple stack underflow).
HARD AND SOFT TRAPS
Preliminary
Each hard trap that occurs must be acknowledged
before code execution of any type may continue. If a
lower priority hard trap occurs while a higher priority
trap is pending, acknowledged, or is being processed,
a hard trap conflict will occur. The conflict occurs
because the lower priority trap cannot be acknowl-
edged until processing for the higher priority trap
completes.
The device is automatically Reset in a hard trap conflict
condition. The TRAPR status bit (RCON<15>) is set
when the Reset occurs, so that the condition may be
detected in software.
In the case of a Math Error Trap or Oscillator Failure
Trap, the condition that causes the trap to occur must
be removed before the respective trap flag bit in the
INTCON1 register may be cleared.
5.4
All interrupt event flags are sampled in the beginning of
each instruction cycle by the IFSx registers. A pending
interrupt request (IRQ) is indicated by the flag bit being
equal to a ‘1’ in an IFSx register. The IRQ will cause an
interrupt to occur if the corresponding bit in the interrupt
enable (IECx) register is set. For the remainder of the
instruction cycle, the priorities of all pending interrupt
requests are evaluated.
If there is a pending IRQ with a priority level greater
than the current processor priority level in the IPL bits,
the processor will be interrupted.
The processor then stacks the current program counter
and the low byte of the processor status register (SRL),
as shown in Figure 5-1. The low byte of the status reg-
ister contains the processor priority level at the time,
prior to the beginning of the interrupt cycle. The proces-
sor then loads the priority level for this interrupt into the
status register. This action will disable all lower priority
interrupts until the completion of the Interrupt Service
Routine.
Interrupt Sequence
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