DSPIC30F3013-30I/SO Microchip Technology, DSPIC30F3013-30I/SO Datasheet - Page 26

• Manufacturer Part Number: DSPIC30F3013-30I/SO
• Description: IC DSPIC MCU/DSP 24K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3013-30I/SO

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301330ISO

dsPIC30F
6.
FIGURE 2-7:
7.
FIGURE 2-8:
8.
DS70082G-page 24
1. PUSH DOEND
2. DO LABEL,#COUNT
2a.Second Word
3. 1st Instruction of Loop
1. MOV.b W0,[W1]
2. MOV.b [W1],PORTB
2a.Stall (NOP)
3. MOV.b W0,PORTB
Two-word instructions for DO. In these instruc-
tions, the fetch after the instruction contains an
address offset. This address offset is added to
the first instruction address to generate the last
loop instruction address. Therefore, these
instructions require 2 cycles, as shown in
Figure 2-7.
Instructions that are subjected to a stall due to a
data dependency between the X RAGU and X
WAGU. An additional cycle is inserted to resolve
the resource conflict, as shown in Figure 2-8.
Instruction stalls caused by data dependencies
are further discussed in Section 4.0.
Interrupt
Section 5.0 for details on interrupts.
recognition
INSTRUCTION PIPELINE FLOW: 2-WORD, 2-CYCLE DO, DOW
INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE WITH INSTRUCTION STALL
Fetch 1
T
Fetch 1
execution.
CY
T
0
CY
0
Execute 1
Fetch 2L
T
Execute 1
Fetch 2
Refer
CY
T
1
CY
1
to
Preliminary
NOP
Fetch 2H
T
NOP
Stall
CY
T
2
CY
2
Execute 2
Execute 2
Fetch 3
T
Fetch 3
CY
T
3
CY
3
Execute 3
T
Execute 3
CY
4
T
 2004 Microchip Technology Inc.
CY
4
T
CY
5