MC9RS08KA2CSCR Freescale Semiconductor, MC9RS08KA2CSCR Datasheet - Page 105

• Manufacturer Part Number: MC9RS08KA2CSCR
• Description: IC MCU 8BIT 2K FLASH 8-SOIC
• Manufacturer: Freescale Semiconductor
• Series: RS08r

Specifications of MC9RS08KA2CSCR

• Core Processor: RS08
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, WDT
• Number Of I /o: 4
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 63 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: RS08KA
• Core: RS08
• Data Bus Width: 8 bit
• Data Ram Size: 63 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: DEMO9RS08KA8, DEMO9RS08KA2
• Minimum Operating Temperature: - 40 C
• For Use With: DEMO9RS08KA2 - DEMO BOARD FOR 9RS08KA2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

12.5
BDC commands are sent serially from a host computer to the BKGD pin of the target MCU. All commands
and data are sent MSB-first using a custom BDC communications protocol. Active background mode
commands require that the target MCU is currently in the active background mode while non-intrusive
commands may be issued at any time whether the target MCU is in active background mode or running a
user application program.
Table 12-2
meaning of each command.
Coding Structure Nomenclature
The following nomenclature is used in
1. The RS08 CPU uses only 14 bits of address and occupies the lower 14 bits of the 16-bit AAAA address field. The values of
address bits 15 and 14 in AAAA are truncated and thus do not matter.
Freescale Semiconductor
soft-reset
WBKP
Reset
WD16
RBKP
AAAA
RD16
Any
WD
W
RD
CC
R
SS
RS08 BDC Commands
d
/
shows all RS08 BDC commands, a shorthand description of their coding structure, and the
15
0
0
=
=
=
=
=
=
=
=
=
=
=
=
= Unimplemented or Reserved
14
0
0
Commands begin with an 8-bit command code in the host-to-target direction
(most significant bit first)
Delay 16 to 511 target BDC clock cycles
Delay of at least 512 BDC clock cycles from last host falling-edge
16-bit address in the host-to-target direction
Eight bits of read data in the target-to-host direction
16 bits of read data in the target-to-host direction
16 bits of write data in the host-to-target direction
the contents of BDCSCR in the target-to-host direction (STATUS)
register)
16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint
register)
Separates parts of the command
Eight bits of write data in the host-to-target direction
Eight bits of write data for BDCSCR in the host-to-target direction (CONTROL)
16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint
A13
13
0
Figure 12-7. BDC Breakpoint Match Register (BDCBKPT)
A12
12
0
MC9RS08KA2 Series Data Sheet, Rev. 4
A11
11
0
Table 12-2
A10
10
0
A9
0
9
to describe the coding structure of the BDC commands.
A8
0
8
A7
0
7
A6
0
6
1
A5
0
5
A4
Chapter 12 Development Support
0
4
A3
0
3
A2
0
2
A1
1
0
105
A0
0
0