MC9RS08KA2CSCR Freescale Semiconductor, MC9RS08KA2CSCR Datasheet - Page 69

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MC9RS08KA2CSCR

Manufacturer Part Number
MC9RS08KA2CSCR
Description
IC MCU 8BIT 2K FLASH 8-SOIC
Manufacturer
Freescale Semiconductor
Series
RS08r
Datasheet

Specifications of MC9RS08KA2CSCR

Core Processor
RS08
Core Size
8-Bit
Speed
10MHz
Peripherals
LVD, POR, WDT
Number Of I /o
4
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
63 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
RS08KA
Core
RS08
Data Bus Width
8 bit
Data Ram Size
63 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
DEMO9RS08KA8, DEMO9RS08KA2
Minimum Operating Temperature
- 40 C
For Use With
DEMO9RS08KA2 - DEMO BOARD FOR 9RS08KA2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
 Details
Freescale Semiconductor
BRSET n,opr8a,rel
BRSET n,D[X],rel
BRSET n,X,rel
BSET n,opr8a
BSET n,D[X]
BSET n,X
1. This is a pseudo instruction supported by the normal RS08 instruction set.
2. This instruction is different from that of the HC08 and HCS08 in that the RS08 does not auto-increment the index register.
Source
Form
Branch if Bit n in Memory
Set
Set Bit n in Memory
Description
Table 8-1. Instruction Set Summary (Sheet 3 of 6)
MC9RS08KA2 Series Data Sheet, Rev. 4
PC ← (PC) + $0003 + rel, if (Mn) = 1
Operation
Mn ← 1
Chapter 8 Central Processor Unit (RS08CPUV1)
— —
Effect
Z
CCR
on
C
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
IX (b0)
IX (b1)
IX (b2)
IX (b3)
IX (b4)
IX (b5)
IX (b6)
IX (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
IX (b0)
IX (b1)
IX (b2)
IX (b3)
IX (b4)
IX (b5)
IX (b6)
IX (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
00
02
04
06
08
0A
0C
0E
00
02
04
06
08
0A
0C
0E
10
12
14
16
18
1A
1C
1E
10
12
14
16
18
1A
1C
1E
10
12
14
16
18
1A
1C
1E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
0E rr
0E rr
0E rr
0E rr
0E rr
0E rr
0E rr
0E rr
0F rr
0F rr
0F rr
0F rr
0F rr
0F rr
0F rr
0F rr
dd
dd
dd
dd
dd
dd
dd
dd
0E
0E
0E
0E
0E
0E
0E
0E
0F
0F
0F
0F
0F
0F
0F
0F
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5
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5
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5
5
5
5
5
5
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5
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