MC9RS08KA2CSCR Freescale Semiconductor, MC9RS08KA2CSCR Datasheet - Page 67

• Manufacturer Part Number: MC9RS08KA2CSCR
• Description: IC MCU 8BIT 2K FLASH 8-SOIC
• Manufacturer: Freescale Semiconductor
• Series: RS08r

Specifications of MC9RS08KA2CSCR

• Core Processor: RS08
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, WDT
• Number Of I /o: 4
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 63 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: RS08KA
• Core: RS08
• Data Bus Width: 8 bit
• Data Ram Size: 63 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: DEMO9RS08KA8, DEMO9RS08KA2
• Minimum Operating Temperature: - 40 C
• For Use With: DEMO9RS08KA2 - DEMO BOARD FOR 9RS08KA2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
ADC #opr8i
ADC opr8a
ADC ,X
ADC X
ADD #opr8i
ADD opr8a
ADD opr4a
ADD ,X
ADD X
AND #opr8i
AND opr8a
AND ,X
AND X
ASLA
BCC rel
BCLR n,opr8a
BCLR n,D[X]
BCLR n,X
BCS rel
BEQ rel
BGND
1. This is a pseudo instruction supported by the normal RS08 instruction set.
2. This instruction is different from that of the HC08 and HCS08 in that the RS08 does not auto-increment the index register.
(1)
Source
Form
(1)
(1)
(1)
Add with Carry
Add without Carry
Logical AND
Arithmetic Shift Left
Branch if Carry Bit Clear
Clear Bit n in Memory
Branch if Carry Bit Set
(Same as BLO)
Branch if Equal
Background
Description
Table 8-1. Instruction Set Summary (Sheet 1 of 6)
MC9RS08KA2 Series Data Sheet, Rev. 4
PC ← (PC) + $0002 + rel, if (C) = 0
PC ← (PC) + $0002 + rel, if (C) = 1
PC ← (PC) + $0002 + rel, if (Z) = 1
Enter Background Debug Mode
C
A ← (A) + (M) + (C)
A ← (A) + (X) + (C)
b7
A ← (A) + (M)
A ← (A) & (M)
A ← (A) & (X)
Operation
Mn ← 0
b0
0
Chapter 8 Central Processor Unit (RS08CPUV1)
— —
— — REL
— — REL
— — INH
Effect
—
Z
CCR
on
—
—
C
IMM
DIR
IX
DIR
IMM
DIR
TNY
IX
DIR
IMM
DIR
IX
DIR
INH
REL
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
IX (b0)
IX (b1)
IX (b2)
IX (b3)
IX (b4)
IX (b5)
IX (b6)
IX (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
A9
B9
B9
B9
AB
BB
6x
6E
6F
A4
B4
B4
B4
48
34
11
13
15
17
19
1B
1D
1F
11
13
15
17
19
1B
1D
1F
11
13
15
17
19
1B
1D
1F
35
37
BF
ii
dd
0E
0F
ii
dd
ii
dd
0E
0F
rr
dd
dd
dd
dd
dd
dd
dd
dd
0E
0E
0E
0E
0E
0E
0E
0E
0F
0F
0F
0F
0F
0F
0F
0F
rr
rr
67
5+
2
3
3
3
2
3
3
3
3
2
3
3
3
1
3
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
3
3