MC9RS08KA2CSCR Freescale Semiconductor, MC9RS08KA2CSCR Datasheet - Page 62

• Manufacturer Part Number: MC9RS08KA2CSCR
• Description: IC MCU 8BIT 2K FLASH 8-SOIC
• Manufacturer: Freescale Semiconductor
• Series: RS08r

Specifications of MC9RS08KA2CSCR

• Core Processor: RS08
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, WDT
• Number Of I /o: 4
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 63 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: RS08KA
• Core: RS08
• Data Bus Width: 8 bit
• Data Ram Size: 63 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: DEMO9RS08KA8, DEMO9RS08KA2
• Minimum Operating Temperature: - 40 C
• For Use With: DEMO9RS08KA2 - DEMO BOARD FOR 9RS08KA2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

Chapter 8 Central Processor Unit (RS08CPUV1)
expression in the operand field of the branch instruction; the assembler calculates the difference between
the location counter (which points at the next address after the branch instruction at the time) and the
address represented by the label or expression in the operand field. This difference is called the offset and
is an 8-bit two’s complement number. The assembler stores this offset in the object code for the branch
instruction.
During execution, the CPU evaluates the condition that controls the branch. If the branch condition is true,
the CPU sign-extends the offset to a 14-bit value, adds the offset to the current PC, and uses this as the
address where it will fetch the next instruction and continue execution rather than continuing execution
with the next instruction after the branch. Because the offset is an 8-bit two’s complement value, the
destination must be within the range –128 to +127 locations from the address that follows the last byte of
object code for the branch instruction.
A common method to create a simple infinite loop is to use a branch instruction that branches to itself. This
is sometimes used to end short code segments during debug. Typically, to get out of this infinite loop, use
the debug host (through background commands) to stop the program, examine registers and memory, or
to start execution from a new location. This construct is not used in normal application programs except
in the case where the program has detected an error and wants to force the COP watchdog timer to timeout.
(The branch in the infinite loop executes repeatedly until the watchdog timer eventually causes a reset.)
8.3.3
In this addressing mode, the operand is located immediately after the opcode in the instruction stream. This
addressing mode is used when the programmer wants to use an explicit value that is known at the time the
program is written. A # (pound) symbol is used to tell the assembler to use the operand as a data value
rather than an address where the desired value will be accessed.
The size of the immediate operand is always 8 bits. The assembler automatically will truncate or extend
the operand as needed to match the size needed for the instruction. Most assemblers generate a warning if
a 16-bit operand is provided.
It is the programmer’s responsibility to use the # symbol to tell the assembler when immediate addressing
will be used. The assembler does not consider it an error to leave off the # symbol because the resulting
statement is still a valid instruction (although it may mean something different than the programmer
intended).
8.3.4
TNY addressing mode is capable of addressing only the first 16 bytes in the address map, from $0000 to
$000F. This addressing mode is available for INC, DEC, ADD, and SUB instructions. A system can be
optimized by placing the most computation-intensive data in this area of memory.
Because the 4-bit address is embedded in the opcode, only the least significant four bits of the address must
be included in the instruction; this saves program space and execution time. During execution, the CPU
adds 10 high-order 0s to the 4-bit operand address and uses the combined 14-bit address ($000x) to access
the intended operand.
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Immediate Addressing Mode (IMM)
Tiny Addressing Mode (TNY)
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor