MC9RS08KA2CSCR Freescale Semiconductor, MC9RS08KA2CSCR Datasheet - Page 78

• Manufacturer Part Number: MC9RS08KA2CSCR
• Description: IC MCU 8BIT 2K FLASH 8-SOIC
• Manufacturer: Freescale Semiconductor
• Series: RS08r

Specifications of MC9RS08KA2CSCR

• Core Processor: RS08
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, WDT
• Number Of I /o: 4
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 63 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: RS08KA
• Core: RS08
• Data Bus Width: 8 bit
• Data Ram Size: 63 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: DEMO9RS08KA8, DEMO9RS08KA2
• Minimum Operating Temperature: - 40 C
• For Use With: DEMO9RS08KA2 - DEMO BOARD FOR 9RS08KA2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

Internal Clock Source (RS08ICSV1)
9.3.2
78
IREFSTEN
CLKS
Field
Field
BDIV
7:6
LP
6
0
3
Reset:
Reset:
W
W
R
R
ICS Control Register 2 (ICSC2)
Clock Source Select — Selects the clock source that controls the bus frequency. The actual bus frequency
depends on the value of the BDIV bits.
0 Output of FLL is selected
1 Internal reference clock is selected
Internal Reference Stop Enable — Controls whether the internal reference clock remains enabled when the
ICS enters stop mode.
1 Internal reference clock remains enabled in stop
0 Internal reference clock is disabled in stop
Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bit. This
controls the bus frequency.
00 Encoding 0 — Divides selected clock by 1
01 Encoding 1 — Divides selected clock by 2 (reset default)
10 Encoding 2 — Divides selected clock by 4
11 Encoding 3 — Divides selected clock by 8
Low Power Select — Controls whether the FLL is disabled in FLL bypassed modes.
1 FLL is disabled in bypass modes
0 FLL is not disabled in bypass mode
0
7
7
0
0
BDIV
= Unimplemented
= Unimplemented
CLKS
1
6
0
6
Figure 9-3. ICS Control Register 1 (ICSC1)
Figure 9-4. ICS Control Register 2 (ICSC2)
MC9RS08KA2 Series Data Sheet, Rev. 4
Table 9-2. ICSC1 Field Descriptions
Table 9-3. ICSC2 Field Descriptions
0
5
0
0
0
5
0
0
4
0
0
4
Description
Description
LP
3
0
0
0
3
0
0
2
0
0
2
Freescale Semiconductor
1
0
0
0
0
1
IREFSTEN
0
0
0
0
0