MC9RS08KA2CSCR Freescale Semiconductor, MC9RS08KA2CSCR Datasheet - Page 76

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MC9RS08KA2CSCR

Manufacturer Part Number
MC9RS08KA2CSCR
Description
IC MCU 8BIT 2K FLASH 8-SOIC
Manufacturer
Freescale Semiconductor
Series
RS08r
Datasheet

Specifications of MC9RS08KA2CSCR

Core Processor
RS08
Core Size
8-Bit
Speed
10MHz
Peripherals
LVD, POR, WDT
Number Of I /o
4
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
63 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
RS08KA
Core
RS08
Data Bus Width
8 bit
Data Ram Size
63 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
DEMO9RS08KA8, DEMO9RS08KA2
Minimum Operating Temperature
- 40 C
For Use With
DEMO9RS08KA2 - DEMO BOARD FOR 9RS08KA2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
 Details
Internal Clock Source (RS08ICSV1)
9.1.1
Key features of the ICS module are:
9.1.2
There are four modes of operation for the ICS: FEI, FBI, FBILP, and stop.
9.1.2.1
In FLL engaged internal mode, which is the default mode, the ICS supplies a clock derived from the FLL
which is controlled by the internal reference clock.
9.1.2.2
In FLL bypassed internal mode, the FLL is enabled and controlled by the internal reference clock, but is
bypassed. The ICS supplies a clock derived from the internal reference clock.
9.1.2.3
In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the internal reference clock.
9.1.2.4
In stop mode, the FLL is disabled and the internal reference clocks can be selected to be enabled or
disabled. The ICS does not provide an MCU clock source.
9.1.3
Figure 9-2
76
Frequency-locked loop (FLL) is trimmable for accuracy
— 0.2% resolution using internal 32 kHz reference
— 2% deviation over voltage and temperature using internal 32 kHz reference
— DCO output is 512 times internal reference frequency
Internal reference clock has 9 trim bits available
Internal reference clock can be selected as the clock source for the MCU
Whichever clock is selected as the source can be divided down
— 2 bit select for clock divider is provided (allowable dividers are: 1, 2, 4, and 8)
FLL engaged internal mode is automatically selected out of reset
shows the ICS block diagram.
Features
Modes of Operation
Block Diagram
FLL Engaged Interna
FLL Bypassed Interna
FLL Bypassed Interna
Stop (STOP)
MC9RS08KA2 Series Data Sheet, Rev. 4
l (FEI)
l (FBI)
l Low Power (FBILP)
Freescale Semiconductor

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