MC9RS08KA2CSCR Freescale Semiconductor, MC9RS08KA2CSCR Datasheet - Page 31

• Manufacturer Part Number: MC9RS08KA2CSCR
• Description: IC MCU 8BIT 2K FLASH 8-SOIC
• Manufacturer: Freescale Semiconductor
• Series: RS08r

Specifications of MC9RS08KA2CSCR

• Core Processor: RS08
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, WDT
• Number Of I /o: 4
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 63 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: RS08KA
• Core: RS08
• Data Bus Width: 8 bit
• Data Ram Size: 63 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: DEMO9RS08KA8, DEMO9RS08KA2
• Minimum Operating Temperature: - 40 C
• For Use With: DEMO9RS08KA2 - DEMO BOARD FOR 9RS08KA2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

4.6.4
The MC9RS08KA2 Series includes circuitry to help prevent unauthorized access to the contents of Flash
memory. When security is engaged, Flash is considered a secure resource. The RAM, direct-page registers,
and background debug controller are considered unsecured resources. Attempts to access a secure memory
location through the background debug interface, or whenever BKGDPE is set, are blocked (reads return
all 0s).
Security is engaged or disengaged based on the state of a nonvolatile register bit (SECD) in the FOPT
register. During reset, the contents of the nonvolatile location NVOPT are copied from Flash into the
working FOPT register in high-page register space. A user engages security by programming the NVOPT
location, which can be done at the same time the Flash memory is programmed. Notice the erased state
(SECD = 1) makes the MCU unsecure. When SECD in NVOPT is programmed (SECD = 0), next time
the device is reset via POR, internal reset, or external reset, security is engaged. In order to disengage
security, mass erase must be performed via BDM commands and followed by any reset.
The separate background debug controller can still be used for registers and RAM access. Flash mass erase
is possible by writing to the Flash control register that follows the Flash mass erase procedure listed in
Section 4.6.3, “Flash Mass Erase
Security can always be disengaged through the background debug interface by following these steps:
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3. Write any data to any Flash location, via the high page accessing window $00C0–$00FF. (Prior to
4. Wait for a time, t
5. Set the HVEN bit.
6. Wait for a time t
7. Clear the MASS bit.
8. Wait for a time, t
9. Clear the HVEN bit.
10. After time, t
11. Remove external V
1. Mass erase Flash via background BDM commands or RAM loaded program.
2. Perform reset and the device will boot up with security disengaged.
the data writing operation, the PAGESEL register must be configured correctly to map the high
page accessing window to the any Flash locations).
Security
Flash memory cannot be programmed or erased by software code executed
from Flash locations. To program or erase Flash, commands must be
executed from RAM or BDC commands. User code should not enter wait or
stop during an erase or program sequence.
These operations must be performed in the order shown, but other unrelated
operations may occur between the steps.
rcv
, the memory can be accessed in read mode again.
me
nvs
nvh1
.
PP
.
.
.
Operation,” via BDM commands.
MC9RS08KA2 Series Data Sheet, Rev. 4
NOTE
Chapter 4 Memory
31