MC9RS08KA2CSCR Freescale Semiconductor, MC9RS08KA2CSCR Datasheet - Page 59

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MC9RS08KA2CSCR

Manufacturer Part Number
MC9RS08KA2CSCR
Description
IC MCU 8BIT 2K FLASH 8-SOIC
Manufacturer
Freescale Semiconductor
Series
RS08r
Datasheet

Specifications of MC9RS08KA2CSCR

Core Processor
RS08
Core Size
8-Bit
Speed
10MHz
Peripherals
LVD, POR, WDT
Number Of I /o
4
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
63 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
RS08KA
Core
RS08
Data Bus Width
8 bit
Data Ram Size
63 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
DEMO9RS08KA8, DEMO9RS08KA2
Minimum Operating Temperature
- 40 C
For Use With
DEMO9RS08KA2 - DEMO BOARD FOR 9RS08KA2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
 Details
8.2.2
The program counter is a 14-bit register that contains the address of the next instruction or operand to be
fetched.
During normal execution, the program counter automatically increments to the next sequential memory
location each time an instruction or operand is fetched. Jump, branch, and return operations load the
program counter with an address other than that of the next sequential location. This is called a
change-of-flow.
During reset, the program counter is loaded with $3FFD and the program will start execution from this
specific location.
8.2.3
The shadow program counter is a 14-bit register. During a subroutine call using either a JSR or a BSR
instruction, the return address will be saved into the SPC. Upon completion of the subroutine, the RTS
instruction will restore the content of the program counter from the shadow program counter.
During reset, the shadow program counter is loaded with $3FFD.
8.2.4
The 2-bit condition code register contains two status flags. The content of the CCR in the RS08 is not
directly readable. The CCR bits can be tested using conditional branch instructions such as BCC and BEQ.
These two register bits are directly accessible through the BDC interface. The following paragraphs
provide detailed information about the CCR bits and how they are used.
and their bit positions.
The status bits (Z and C) are cleared to 0 after reset.
The two status bits indicate the results of arithmetic and other instructions. Conditional branch instructions
will either branch to a new program location or allow the program to continue to the next instruction after
the branch, depending on the values in the CCR status bit. Conditional branch instructions, such as BCC,
BCS, and BNE, cause a branch depending on the state of a single CCR bit.
Often, the conditional branch immediately follows the instruction that caused the CCR bit(s) to be updated,
as in this sequence:
more:
lower:
Freescale Semiconductor
deca
cmp
blo
Program Counter (PC)
Shadow Program Counter (SPC)
Condition Code Register (CCR)
#5
lower
;do this if A not higher than or same as 5
;compare accumulator A to 5
;branch if A smaller 5
CONDITION CODE REGISTER
Figure 8-3. Condition Code Register (CCR)
MC9RS08KA2 Series Data Sheet, Rev. 4
Z
C
Chapter 8 Central Processor Unit (RS08CPUV1)
CARRY
ZERO
CCR
Figure 8-3
identifies the CCR bits
59

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