MC9RS08KA2CSCR Freescale Semiconductor, MC9RS08KA2CSCR Datasheet - Page 65

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MC9RS08KA2CSCR

Manufacturer Part Number
MC9RS08KA2CSCR
Description
IC MCU 8BIT 2K FLASH 8-SOIC
Manufacturer
Freescale Semiconductor
Series
RS08r
Datasheet

Specifications of MC9RS08KA2CSCR

Core Processor
RS08
Core Size
8-Bit
Speed
10MHz
Peripherals
LVD, POR, WDT
Number Of I /o
4
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
63 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
RS08KA
Core
RS08
Data Bus Width
8 bit
Data Ram Size
63 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
DEMO9RS08KA8, DEMO9RS08KA2
Minimum Operating Temperature
- 40 C
For Use With
DEMO9RS08KA2 - DEMO BOARD FOR 9RS08KA2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
 Details
8.5
Instruction Set Summary Nomenclature
The nomenclature listed here is used in the instruction descriptions in
Operators
CPU registers
Memory and addressing
,X or D[X] =
Condition code register (CCR) bits
CCR activity notation
Machine coding notation
Freescale Semiconductor
SPCH
SPCL
CCR
PCH
SPC
PCL
PC
rel
M =
( )
X =
C
U
&
A
Z
Summary Instruction Table
+
0
1
|
:
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
Contents of register or memory location shown inside parentheses
Is loaded with (read: “gets”)
Exchange with
Boolean AND
Boolean OR
Boolean exclusive-OR
Concatenate
Add
Accumulator
Program counter, lower order (least significant) eight bits
A memory location or absolute data, depending on addressing mode
The relative offset, which is the two’s complement number stored in the last
byte of machine code corresponding to a branch instruction
Pseudo index register, memory location $000F
Memory location $000E pointing to the memory location defined by the
pseudo index register (location $000F)
Zero indicator
Carry/borrow
Bit not affected
Bit forced to 0
Bit forced to 1
Bit set or cleared according to results of operation
Undefined after the operation
Condition code register
Program counter
Program counter, higher order (most significant) six bits
Shadow program counter
Shadow program counter, higher order (most significant) six bits
Shadow program counter, lower order (least significant) eight bits
MC9RS08KA2 Series Data Sheet, Rev. 4
Chapter 8 Central Processor Unit (RS08CPUV1)
Table 8-1
through
Table
8-2.
65

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