MC9RS08KA2CSCR Freescale Semiconductor, MC9RS08KA2CSCR Datasheet - Page 73

• Manufacturer Part Number: MC9RS08KA2CSCR
• Description: IC MCU 8BIT 2K FLASH 8-SOIC
• Manufacturer: Freescale Semiconductor
• Series: RS08r

Specifications of MC9RS08KA2CSCR

• Core Processor: RS08
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: LVD, POR, WDT
• Number Of I /o: 4
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 63 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: RS08KA
• Core: RS08
• Data Bus Width: 8 bit
• Data Ram Size: 63 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: DEMO9RS08KA8, DEMO9RS08KA2
• Minimum Operating Temperature: - 40 C
• For Use With: DEMO9RS08KA2 - DEMO BOARD FOR 9RS08KA2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
LOW
INH
IMM
DIR
EXT
DD
HIGH
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
BRSET0
BRCLR0
BRSET1
BRCLR1
BRSET2
BRCLR2
BRSET3
BRCLR3
BRSET4
BRCLR4
BRSET5
BRCLR5
BRSET6
BRCLR6
BRSET7
BRCLR7
Inherent
Immediate
Direct
Extended
Direct-Direct
DIR
0
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Gray box is decoded as illegal instruction
BSET0
BCLR0
BSET1
BCLR1
BSET2
BCLR2
BSET3
BCLR3
BSET4
BCLR4
BSET5
BCLR5
BSET6
BCLR6
BSET7
BCLR7
DIR
1
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
REL
SRT
TNY
IMD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TNY
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
2
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
Relative
Short
Tiny
Immediate-Direct
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
3
2
2
2
2
1
1
2
3
2
3
2
DIR/REL
CBEQ
DBNZ
BCC
BEQ
DEC
MOV
BRA
BCS
BNE
CLC
SEC
CLR
INC
3
REL
REL
REL
REL
REL
IMD
DIR
INH
INH
DIR
DIR
DIR
DIR
3
5
3
3
3
3
1
1
5
6
5
4
3
3
1
1
1
1
1
1
1
1
2
1
3
1
CBEQA
DBNZA
COMA
RORA
ROLA
DECA
CLRA
LSRA
LSLA
INCA
MOV
SHA
SLA
INH
4
IMM
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
DD
MC9RS08KA2 Series Data Sheet, Rev. 4
4
1
1
1
1
1
1
1
1
4
1
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
TNY
5
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Table 8-2. Opcode Map
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
TNY
6
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
TNY
7
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
TNY
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
SRT
8
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
Low Byte of Opcode in Hexadecimal
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
CLR
SRT
9
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
High Byte of Opcode in Hexadecimal
Chapter 8 Central Processor Unit (RS08CPUV1)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
1
1
IMM/INH
STOP
WAIT
CMP
EOR
ORA
NOP
SUB
SBC
AND
ADC
ADD
BSR
LDA
A
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
REL
INH
INH
INH
2+
2+
2
2
2
2
2
2
2
2
2
1
3
2
2
2
2
2
2
2
2
2
2
3
3
1
1
DIR/EXT
BGND
CMP
SUB
SBC
AND
EOR
ADC
ORA
ADD
LDA
JMP
JSR
RTS
STA
B
EXT
EXT
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
INH
INH
5+
3
3
3
3
3
3
3
3
3
3
4
4
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA
SRT
C
0
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
SUB
LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA
SRT
D
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
DIR
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RS08 Cycles
Opcode Mnemonic
Number of Bytes /
Addressing Mode
STA
STA
STA
STA
STA
STA
STA
STA
STA
STA
STA
STA
STA
STA
STA
STA
SRT
E
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
73
STA
STA
STA
STA
STA
STA
STA
STA
STA
STA
STA
STA
STA
STA
STA
STA
SRT
F
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
SRT
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2