MC9S08JM16CGT Freescale Semiconductor, MC9S08JM16CGT Datasheet - Page 143

• Manufacturer Part Number: MC9S08JM16CGT
• Description: MCU 8BIT 16K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08JM16CGT

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SCI, SPI, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S08JM
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Controller Family/series: HCS08
• No. Of I/o's: 37
• Ram Memory Size: 1KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Digital Ic Case Style: QFN
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.3.6
This register holds the lower 8 bits of the 12-bit or 10-bit compare value or all 8 bits of the 8-bit compare
value. When the compare function is enabled, bits ADCV[7:0] are compared to the lower 8 bits of the
result following a conversion in 12-bit, 10-bit or 8-bit mode.
10.3.7
ADCCFG selects the mode of operation, clock source, clock divide, and configures for low power and long
sample time.
Freescale Semiconductor
ADLSMP
ADICLK
ADLPC
MODE
Field
ADIV
6:5
3:2
1:0
7
4
Reset:
Reset:
W
W
R
R
Compare Value Low Register (ADCCVL)
Configuration Register (ADCCFG)
Low-Power Configuration. ADLPC controls the speed and power configuration of the successive approximation
converter. This optimizes power consumption when higher sample rates are not required.
0 High speed configuration
1 Low power configuration:The power is reduced at the expense of maximum clock speed.
Clock Divide Select. ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK.
Table 10-7
Long Sample Time Configuration. ADLSMP selects between long and short sample time. This adjusts the
sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for
lower impedance inputs. Longer sample times can also be used to lower overall power consumption when
continuous conversions are enabled if high conversion rates are not required.
0 Short sample time
1 Long sample time
Conversion Mode Selection. MODE bits are used to select between 12-, 10-, or 8-bit operation. See
Input Clock Select. ADICLK bits select the input clock source to generate the internal clock ADCK. See
Table
ADCV7
ADLPC
10-9.
7
0
7
0
shows the available clock configurations.
ADCV6
Figure 10-8. Compare Value Low Register (ADCCVL)
Table 10-6. ADCCFG Register Field Descriptions
0
0
6
6
Figure 10-9. Configuration Register (ADCCFG)
ADIV
MC9S08JM16 Series Data Sheet, Rev. 2
ADCV5
0
0
5
5
ADLSMP
ADCV4
0
0
4
4
Description
ADCV3
0
0
3
3
MODE
ADCV2
Analog-to-Digital Converter (S08ADC12V1)
0
0
2
2
ADCV1
0
0
1
1
ADICLK
ADCV0
Table
0
0
0
0
10-8.
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