MC9S08JM16CGT Freescale Semiconductor, MC9S08JM16CGT Datasheet - Page 96

• Manufacturer Part Number: MC9S08JM16CGT
• Description: MCU 8BIT 16K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08JM16CGT

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SCI, SPI, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S08JM
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Controller Family/series: HCS08
• No. Of I/o's: 37
• Ram Memory Size: 1KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Digital Ic Case Style: QFN
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 6 Parallel Input/Output
6.5.14
In addition to the I/O control, port G pins are controlled by the registers listed below.
96
PTGPEn
PTGSEn
Reset
Reset
Field
Field
5:0
5:0
W
W
R
R
Port G Pin Control Registers (PTGPE, PTGSE, PTGDS)
Internal Pullup Enable for Port G Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTG pin. For port G pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port G bit n.
1 Internal pullup device enabled for port G bit n.
Output Slew Rate Control Enable for Port G Bits— Each of these control bits determine whether output slew
rate control is enabled for the associated PTG pin. For port G pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port G bit n.
1 Output slew rate control enabled for port G bit n.
0
0
7
7
Figure 6-35. Output Slew Rate Control Enable for Port G Bits (PTGSE)
Figure 6-34. Internal Pullup Enable for Port G Bits (PTGPE)
0
0
6
6
Table 6-34. PTGSE Register Field Descriptions
Table 6-33. PTGPE Register Field Descriptions
PTGPE5
PTGSE5
MC9S08JM16 Series Data Sheet, Rev. 2
0
1
5
5
PTGPE4
PTGSE4
0
1
4
4
Description
Description
PTGPE3
PTGSE3
3
0
3
1
PTGPE2
PTGSE2
0
1
2
2
PTGPE1
PTGSE1
Freescale Semiconductor
0
1
1
1
PTGPE0
PTGSE0
0
1
0
0