MC9S08JM16CGT Freescale Semiconductor, MC9S08JM16CGT Datasheet - Page 276

MCU 8BIT 16K FLASH 48-QFN

MC9S08JM16CGT

Manufacturer Part Number
MC9S08JM16CGT
Description
MCU 8BIT 16K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08JM16CGT

Core Processor
HCS08
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SCI, SPI, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S08JM
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
Controller Family/series
HCS08
No. Of I/o's
37
Ram Memory Size
1KB
Cpu Speed
48MHz
No. Of Timers
2
Digital Ic Case Style
QFN
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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16.3
This section consists of register descriptions in address order. A typical MCU system may contain multiple
TPMs, and each TPM may have one to eight channels, so register names include placeholder characters to
identify which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer
(TPM) x, channel n. TPM1C2SC would be the status and control register for channel 2 of timer 1.
16.3.1
TPMxSC contains the overflow status flag and control bits used to configure the interrupt enable, TPM
configuration, clock source, and prescale factor. These controls relate to all channels within this timer
module.
276
Reset
CPWMS
Field
TOIE
TOF
W
7
6
5
R
Register Definition
TOF
Timer overflow flag. This read/write flag is set when the TPM counter resets to 0x0000 after reaching the modulo
value programmed in the TPM counter modulo registers. Clear TOF by reading the TPM status and control
register when TOF is set and then writing a logic 0 to TOF. If another TPM overflow occurs before the clearing
sequence is complete, the sequence is reset so TOF would remain set after the clear sequence was completed
for the earlier TOF. This is done so a TOF interrupt request cannot be lost during the clearing sequence for a
previous TOF. Reset clears TOF. Writing a logic 1 to TOF has no effect.
0 TPM counter has not reached modulo value or overflow
1 TPM counter has overflowed
Timer overflow interrupt enable. This read/write bit enables TPM overflow interrupts. If TOIE is set, an interrupt is
generated when TOF equals one. Reset clears TOIE.
0 TOF interrupts inhibited (use for software polling)
1 TOF interrupts enabled
Center-aligned PWM select. When present, this read/write bit selects CPWM operating mode. By default, the TPM
operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting
CPWMS reconfigures the TPM to operate in up/down counting mode for CPWM functions. Reset clears CPWMS.
0 All channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the
1 All channels operate in center-aligned PWM mode.
TPM Status and Control Register (TPMxSC)
0
0
7
MSnB:MSnA control bits in each channel’s status and control register.
TOIE
0
6
Figure 16-7. TPM Status and Control Register (TPMxSC)
Table 16-2. TPMxSC Field Descriptions
CPWMS
MC9S08JM16 Series Data Sheet, Rev. 2
5
0
CLKSB
0
4
Description
CLKSA
0
3
PS2
0
2
PS1
Freescale Semiconductor
1
0
PS0
0
0

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