MC9S08JM16CGT Freescale Semiconductor, MC9S08JM16CGT Datasheet - Page 17

• Manufacturer Part Number: MC9S08JM16CGT
• Description: MCU 8BIT 16K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08JM16CGT

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SCI, SPI, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S08JM
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Controller Family/series: HCS08
• No. Of I/o's: 37
• Ram Memory Size: 1KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Digital Ic Case Style: QFN
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.2 External Signal Description ..........................................................................................................300
17.3 Register Definition ........................................................................................................................300
17.4 Functional Description ..................................................................................................................311
18.1 Introduction ...................................................................................................................................327
18.2 Background Debug Controller (BDC) ..........................................................................................328
18.3 On-Chip Debug System (DBG) ....................................................................................................337
Freescale Semiconductor
17.2.1 USBDP ............................................................................................................................300
17.2.2 USBDN ...........................................................................................................................300
17.2.3 V
17.3.1 USB Control Register 0 (USBCTL0) .............................................................................301
17.3.2 Peripheral ID Register (PERID) .....................................................................................301
17.3.3 Peripheral ID Complement Register (IDCOMP) ............................................................302
17.3.4 Peripheral Revision Register (REV) ...............................................................................302
17.3.5 Interrupt Status Register (INTSTAT) ..............................................................................303
17.3.6 Interrupt Enable Register (INTENB) ..............................................................................304
17.3.7 Error Interrupt Status Register (ERRSTAT) ...................................................................305
17.3.8 Error Interrupt Enable Register (ERRENB) ...................................................................306
17.3.9 Status Register (STAT) ....................................................................................................307
17.3.10Control Register (CTL) ...................................................................................................308
17.3.11Address Register (ADDR) ..............................................................................................309
17.3.12Frame Number Register (FRMNUML, FRMNUMH) ...................................................309
17.3.13Endpoint Control Register (EPCTLn, n=0-6) .................................................................310
17.4.1 Block Descriptions ..........................................................................................................311
17.4.2 Buffer Descriptor Table (BDT) .......................................................................................316
17.4.3 USB Transactions ...........................................................................................................319
17.4.4 USB Packet Processing ...................................................................................................321
17.4.5 Start of Frame Processing ...............................................................................................322
17.4.6 Suspend/Resume .............................................................................................................323
17.4.7 Resets ..............................................................................................................................324
17.4.8 Interrupts .........................................................................................................................325
18.1.1 Forcing Active Background ............................................................................................327
18.1.2 Features ...........................................................................................................................328
18.2.1 BKGD Pin Description ...................................................................................................329
18.2.2 Communication Details ..................................................................................................330
18.2.3 BDC Commands .............................................................................................................334
18.2.4 BDC Hardware Breakpoint .............................................................................................336
18.3.1 Comparators A and B .....................................................................................................337
18.3.2 Bus Capture Information and FIFO Operation ...............................................................337
18.3.3 Change-of-Flow Information ..........................................................................................338
18.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................338
18.3.5 Trigger Modes .................................................................................................................339
18.3.6 Hardware Breakpoints ....................................................................................................341
USB33 ............................................................................................................................................................. 300
MC9S08JM16 Series Data Sheet, Rev. 2
Development Support
Chapter 18
17