MC9S08JM16CGT Freescale Semiconductor, MC9S08JM16CGT Datasheet - Page 365

• Manufacturer Part Number: MC9S08JM16CGT
• Description: MCU 8BIT 16K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08JM16CGT

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SCI, SPI, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S08JM
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Controller Family/series: HCS08
• No. Of I/o's: 37
• Ram Memory Size: 1KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Digital Ic Case Style: QFN
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

A.12.3
Table A-14
Freescale Semiconductor
Num
10
11
12
and
SPI Characteristics
1
2
3
4
5
6
7
8
9
1
Figure A-10
C
D
D
D
D
D
D
D
D
D
D
D
D
Operating frequency
Cycle time
Enable lead time
Enable lag time
Clock (SPSCK) high time Master and
Slave
Clock (SPSCK) low time Master and
Slave
Data setup time (inputs)
Data hold time (inputs)
Access time, slave
Disable time, slave
Data setup time (outputs)
Data hold time (outputs)
TPMxCHn
TPMxCHn
through
Characteristic
Table A-14. SPI Electrical Characteristic
Figure A-9. Timer Input Capture Pulse
MC9S08JM16 Series Data Sheet, Rev. 2
Figure A-13
3
4
2
Master
Master
Master
Master
Master
Master
Master
Master
describe the timing requirements for the SPI system.
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
t
t
ICPW
ICPW
Symbol
t
t
t
t
t
t
t
t
t
t
SCKH
SCKL
HI(M)
t
t
SI(M)
HI(S)
Lead
Lead
SI(S)
t
t
t
t
SCK
SCK
t
f
f
Lag
Lag
HO
HO
t
SO
SO
op
op
dis
A
1/2 t
1/2 t
f
Bus
SCK
SCK
Min
–10
–10
DC
1/2
1/2
30
30
30
30
25
25
—
—
—
/2048
2
4
0
– 25
– 25
Appendix A Electrical Characteristics
f
f
2048
Max
Bus
Bus
1/2
1/2
40
40
—
—
—
—
—
—
—
—
—
—
—
—
—
/2
/4
Unit
t
t
t
t
t
t
SCK
SCK
SCK
SCK
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
365