MC9S08JM16CGT Freescale Semiconductor, MC9S08JM16CGT Datasheet - Page 72

• Manufacturer Part Number: MC9S08JM16CGT
• Description: MCU 8BIT 16K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08JM16CGT

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SCI, SPI, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S08JM
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Controller Family/series: HCS08
• No. Of I/o's: 37
• Ram Memory Size: 1KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Digital Ic Case Style: QFN
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
1
Chapter 5 Resets, Interrupts, and System Configuration
5.7.5
72
COPCLKS
Windowed COP operation requires the user to clear the COP timer in the last 25% of the selected timeout period. This column
displays the minimum number of clock counts required before the COP timer can be reset in windowed COP mode (COPW = 1).
Values shown in milliseconds based on t
tolerance of this value.
This bit can be written only one time after reset. Additional writes are ignored.
Reset
SPI1FE
COPCLKS
COPW
Field
7
6
2
W
N/A
R
0
0
0
1
1
1
COPCLKS
Control Bits
System Options Register 2 (SOPT2)
COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog.
0 Internal 1 KHz LPO clock is source to COP.
1 Bus clock is source to COP.
COP Window — This write-once bit selects the COP operation mode. When set, the 0x55-0xAA write sequence
to the SRS register must occur in the last 25% of the selected period. Any write to the SRS register during the
first 75% of the selected period will reset the MCU.
0 Normal COP operation.
1 Window COP operation.
SPI1 Ports Input Filter Enable
0 Disable input filter on SPI1 port pins to allow for higher maximum SPI baud rate.
1 Enable input filter on SPI1 port pins to eliminate noise and restrict maximum SPI baud rate.
0
7
1
COPT[1:0]
= Unimplemented or Reserved
0:0
0:1
1:0
1:1
0:1
1:0
1:1
COPW
0
6
1
Figure 5-6. System Options Register 2 (SOPT2)
Table 5-7. SOPT2 Register Field Descriptions
Clock Source
Table 5-6. COP Configuration Options
1 kHz LPO
1 kHz LPO
1 kHz LPO
MC9S08JM16 Series Data Sheet, Rev. 2
LPO
BUSCLK
BUSCLK
BUSCLK
clock
clock
clock
N/A
0
0
5
= 1 ms. See t
COP Window
LPO
0
0
4
196,608 cycles
49,152 cycles
Description
(COPW = 1)
6144 cycles
in the appendix
N/A
N/A
N/A
N/A
1
Opens
3
0
0
Section A.12.1, “Control
SPI1FE
1
2
COP Overflow Count
2
2
2
10
8
5
COP is disabled
cycles (256 ms
cycles (32 ms
cycles (1.024 s
2
2
2
Freescale Semiconductor
SPI2FE
13
16
18
cycles
cycles
cycles
1
1
Timing,” for the
2
1
1
)
)
)
ACIC
0
0