C8051F130-GQR Silicon Laboratories Inc, C8051F130-GQR Datasheet - Page 136

• Manufacturer Part Number: C8051F130-GQR
• Description: IC 8051 MCU 128K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F13xr

Specifications of C8051F130-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
and a RET pops two record bits, also.) The stack record circuitry can also detect an overflow or underflow
on the 32-bit shift register, and can notify the debug software even with the MCU running at speed.
11.2.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFR’s). The SFR’s provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFR’s found in a typical 8051 implementation as well as implementing additional
SFR’s used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set. Table 11.2 lists the SFR’s
implemented in the CIP-51 System Controller.
The SFR registers are accessed whenever the direct addressing mode is used to access memory loca-
tions from 0x80 to 0xFF. SFR’s with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, P1, SCON, IE, etc.)
are bit-addressable as well as byte-addressable. All other SFR’s are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the datasheet, as indicated in
Table 11.3, for a detailed description of each register.
11.2.6.1.SFR Paging
The CIP-51 features SFR paging, allowing the device to map many SFR’s into the 0x80 to 0xFF memory
address space. The SFR memory space has 256 pages . In this way, each memory location from 0x80 to
0xFF can access up to 256 SFR’s. The C8051F12x family of devices utilizes five SFR pages: 0, 1, 2, 3,
and F. SFR pages are selected using the Special Function Register Page Selection register, SFRPAGE
(see SFR Definition 11.3). The procedure for reading and writing an SFR is as follows:
11.2.6.2.Interrupts and SFR Paging
When an interrupt occurs, the SFR Page Register will automatically switch to the SFR page containing the
flag bit that caused the interrupt. The automatic SFR Page switch function conveniently removes the bur-
den of switching SFR pages from the interrupt service routine. Upon execution of the RETI instruction, the
SFR page is automatically restored to the SFR Page in use prior to the interrupt. This is accomplished via
a three-byte SFR Page Stack . The top byte of the stack is SFRPAGE, the current SFR Page. The second
byte of the SFR Page Stack is SFRNEXT. The third, or bottom byte of the SFR Page Stack is SFRLAST.
On interrupt, the current SFRPAGE value is pushed to the SFRNEXT byte, and the value of SFRNEXT is
pushed to SFRLAST. Hardware then loads SFRPAGE with the SFR Page containing the flag bit associated
with the interrupt. On a return from interrupt, the SFR Page Stack is popped resulting in the value of SFRN-
EXT returning to the SFRPAGE register, thereby restoring the SFR page context without software interven-
tion. The value in SFRLAST (0x00 if there is no SFR Page value in the bottom of the stack) of the stack is
placed in SFRNEXT register. If desired, the values stored in SFRNEXT and SFRLAST may be modified
during an interrupt, enabling the CPU to return to a different SFR Page upon execution of the RETI instruc-
tion (on interrupt exit). Modifying registers in the SFR Page Stack does not cause a push or pop of the
stack. Only interrupt calls and returns will cause push/pop operations on the SFR Page Stack.
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1. Select the appropriate SFR page number using the SFRPAGE register.
2. Use direct accessing mode to read or write the special function register (MOV instruction).
Rev. 1.4