C8051F130-GQR Silicon Laboratories Inc, C8051F130-GQR Datasheet - Page 6

• Manufacturer Part Number: C8051F130-GQR
• Description: IC 8051 MCU 128K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F13xr

Specifications of C8051F130-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
18. Port Input/Output.................................................................................................. 235
19. System Management Bus / I2C Bus (SMBus0) .................................................. 259
20. Enhanced Serial Peripheral Interface (SPI0)...................................................... 273
6
17.6.EMIF Timing ................................................................................................... 225
18.1.Ports 0 through 3 and the Priority Crossbar Decoder..................................... 238
18.2.Ports 4 through 7 (100-pin TQFP devices only) ............................................. 252
19.1.Supporting Documents ................................................................................... 260
19.2.SMBus Protocol.............................................................................................. 260
19.3.SMBus Transfer Modes.................................................................................. 262
19.4.SMBus Special Function Registers ................................................................ 264
20.1.Signal Descriptions......................................................................................... 274
17.5.3.Split Mode with Bank Select................................................................... 225
17.5.4.External Only.......................................................................................... 225
17.6.1.Non-multiplexed Mode ........................................................................... 227
17.6.2.Multiplexed Mode ................................................................................... 230
18.1.1.Crossbar Pin Assignment and Allocation ............................................... 238
18.1.2.Configuring the Output Modes of the Port Pins...................................... 239
18.1.3.Configuring Port Pins as Digital Inputs................................................... 240
18.1.4.Weak Pullups ......................................................................................... 240
18.1.5.Configuring Port 1 Pins as Analog Inputs .............................................. 240
18.1.6.External Memory Interface Pin Assignments ......................................... 241
18.1.7.Crossbar Pin Assignment Example........................................................ 243
18.2.1.Configuring Ports which are not Pinned Out .......................................... 252
18.2.2.Configuring the Output Modes of the Port Pins...................................... 252
18.2.3.Configuring Port Pins as Digital Inputs................................................... 253
18.2.4.Weak Pullups ......................................................................................... 253
18.2.5.External Memory Interface ..................................................................... 253
19.2.1.Arbitration............................................................................................... 261
19.2.2.Clock Low Extension.............................................................................. 261
19.2.3.SCL Low Timeout................................................................................... 261
19.2.4.SCL High (SMBus Free) Timeout .......................................................... 261
19.3.1.Master Transmitter Mode ....................................................................... 262
19.3.2.Master Receiver Mode ........................................................................... 262
19.3.3.Slave Transmitter Mode ......................................................................... 263
19.3.4.Slave Receiver Mode ............................................................................. 263
19.4.1.Control Register ..................................................................................... 264
19.4.2.Clock Rate Register ............................................................................... 267
19.4.3.Data Register ......................................................................................... 268
19.4.4.Address Register.................................................................................... 268
19.4.5.Status Register....................................................................................... 269
20.1.1.Master Out, Slave In (MOSI).................................................................. 274
20.1.2.Master In, Slave Out (MISO).................................................................. 274
20.1.3.Serial Clock (SCK) ................................................................................. 274
20.1.4.Slave Select (NSS) ................................................................................ 274
Rev. 1.4