C8051F130-GQR Silicon Laboratories Inc, C8051F130-GQR Datasheet - Page 182

• Manufacturer Part Number: C8051F130-GQR
• Description: IC 8051 MCU 128K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F13xr

Specifications of C8051F130-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
182
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
Bit7
R
-
Reserved.
CNVRSEF: Convert Start 0 Reset Source Enable and Flag
Write:
Read:
C0RSEF: Comparator0 Reset Enable and Flag.
Write:
Read:
SWRSF: Software Reset Force and Flag.
Write:
Read:
WDTRSF: Watchdog Timer Reset Flag.
MCDRSF: Missing Clock Detector Flag.
Write:
Read:
PORSF: Power-On Reset Flag.
Write: If the V
be written to select or de-select the V
0: De-select the V
1: Select the V
Important: At power-on, the V
enable pin (MONEN). The PORSF bit does not disable or enable the V
ply selects the V
Read: This bit is set whenever a power-on reset occurs. This may be due to a true power-on reset or a
V
reset.
0: Source of last reset was not a power-on or V
1: Source of last reset was a power-on or V
Note: When this flag is read as '1', all other reset flags are indeterminate.
PINRSF: HW Pin Reset Flag.
Write:
Read:
DD
CNVRSEF C0RSEF SWRSEF WDTRSF MCDRSF
monitor reset. In either case, data memory should be considered indeterminate following the
R/W
Bit6
0: CNVSTR0 is not a reset source.
1: CNVSTR0 is a reset source (active low).
0: Source of prior reset was not CNVSTR0.
1: Source of prior reset was CNVSTR0.
0: Comparator0 is not a reset source.
1: Comparator0 is a reset source (active low).
0: Source of last reset was not Comparator0.
1: Source of last reset was Comparator0.
0: No effect.
1: Forces an internal reset. RST pin is not effected.
0: Source of last reset was not a write to the SWRSF bit.
1: Source of last reset was a write to the SWRSF bit.
0: Source of last reset was not WDT timeout.
1: Source of last reset was WDT timeout.
0: Missing Clock Detector disabled.
1: Missing Clock Detector enabled; triggers a reset if a missing clock condition is detected.
0: Source of last reset was not a Missing Clock Detector timeout.
1: Source of last reset was a Missing Clock Detector timeout.
0: No effect.
1: Forces a Power-On Reset. RST is driven low.
0: Source of prior reset was not RST pin.
1: Source of prior reset was RST pin.
SFR Definition 13.2. RSTSRC: Reset Source
DD
DD
monitor circuitry is enabled (by tying the MONEN pin to a logic high state), this bit can
DD
DD
monitor as a reset source.
R/W
Bit5
monitor as a reset source.
monitor as a reset source.
R/W
Bit4
DD
monitor is enabled/disabled using the external V
DD
Rev. 1.4
monitor as a reset source.
DD
Bit3
R
monitor reset.
DD
monitor reset.
R/W
Bit2
PORSF
R/W
Bit1
DD
SFR Address:
monitor circuit. It sim-
PINRSF
SFR Page:
R/W
Bit0
DD
monitor
0xEF
0
00000000
Reset Value