C8051F130-GQR Silicon Laboratories Inc, C8051F130-GQR Datasheet - Page 297

• Manufacturer Part Number: C8051F130-GQR
• Description: IC 8051 MCU 128K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F13xr

Specifications of C8051F130-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

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*Note:
Bit7:
Bit6:
Bit5:
Bit4:
Bits3–2: UART0 Transmit Baud Rate Clock Selection Bits
Bits1–0: UART0 Receive Baud Rate Clock Selection Bits
FE0
R/W
Bit7
SFR Definition 21.2. SSTA0: UART0 Status and Clock Selection
FE0: Frame Error Flag.*
This flag indicates if an invalid (low) STOP bit is detected.
0: Frame Error has not been detected
1: Frame Error has been detected.
RXOV0: Receive Overrun Flag.*
This flag indicates new data has been latched into the receive buffer before software has
read the previous byte.
0: Receive overrun has not been detected.
1: Receive Overrun has been detected.
TXCOL0: Transmit Collision Flag.*
This flag indicates user software has written to the SBUF0 register while a transmission is
in progress.
0: Transmission Collision has not been detected.
1: Transmission Collision has been detected.
SMOD0: UART0 Baud Rate Doubler Enable.
This bit enables/disables the divide-by-two function of the UART0 baud rate logic for config-
urations described in the UART0 section.
0: UART0 baud rate divide-by-two enabled.
1: UART0 baud rate divide-by-two disabled.
FE0, RXOV0, and TXCOL0 are flags only, and no interrupt is generated by these conditions.
S0TCLK1
S0RCLK1 S0RCLK0
RXOV0 TXCOL0 SMOD0 S0TCLK1 S0TCLK0 S0RCLK1 S0RCLK0 00000000
R/W
Bit6
0
0
1
1
0
0
1
1
S0TCLK0
R/W
Bit5
0
1
0
1
0
1
0
1
R/W
Bit4
Timer 2 Overflow generates UART0 RX baud rate
Timer 3 Overflow generates UART0 RX baud rate
Timer 4 Overflow generates UART0 RX baud rate
Timer 2 Overflow generates UART0 TX baud rate
Timer 3 Overflow generates UART0 TX baud rate
Timer 4 Overflow generates UART0 TX baud rate
Serial Transmit Baud Rate Clock Source
Serial Receive Baud Rate Clock Source
Timer 1 generates UART0 TX Baud Rate
Timer 1 generates UART0 RX Baud Rate
R/W
Bit3
Rev. 1.4
C8051F120/1/2/3/4/5/6/7
R/W
Bit2
R/W
Bit1
C8051F130/1/2/3
SFR Address:
SFR Page:
R/W
Bit0
0x91
0
Reset Value
297