C8051F130-GQR Silicon Laboratories Inc, C8051F130-GQR Datasheet - Page 224

• Manufacturer Part Number: C8051F130-GQR
• Description: IC 8051 MCU 128K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F13xr

Specifications of C8051F130-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
17.5. Memory Mode Selection
The external data memory space can be configured in one of four modes, shown in Figure 17.3, based on
the EMIF Mode bits in the EMI0CF register (SFR Definition 17.2). These modes are summarized below.
More information about the different modes can be found in
External Memory Timing Control” on page 226
17.5.1. Internal XRAM Only
When EMI0CF.[3:2] are set to ‘00’, all MOVX instructions will target the internal XRAM space on the
device. Memory accesses to addresses beyond the populated space will wrap on 8 k boundaries. As an
example, the addresses 0x2000 and 0x4000 both evaluate to address 0x0000 in on-chip XRAM space.
•
•
17.5.2. Split Mode without Bank Select
When EMI0CF.[3:2] are set to ‘01’, the XRAM memory map is split into two areas, on-chip space and off-
chip space.
•
•
•
•
224
EMI0CF[3:2] = 00
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address
and R0 or R1 to determine the low-byte of the effective address.
16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address.
Effective addresses below the 8 k boundary will access on-chip XRAM space.
Effective addresses above the 8 k boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-
chip or off-chip. However, in the “No Bank Select” mode, an 8-bit MOVX operation will not drive the
upper 8-bits A[15:8] of the Address Bus during an off-chip access. This allows the user to manipulate
the upper address bits at will by setting the Port state directly via the port latches. This behavior is in
contrast with “Split Mode with Bank Select” described below. The lower 8-bits of the Address Bus
A[7:0] are driven, determined by R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-
chip or off-chip, and unlike 8-bit MOVX operations, the full 16-bits of the Address Bus A[15:0] are
driven during the off-chip transaction.
0xFFFF
0x0000
EMI0CF[3:2] = 01
(No Bank Select)
On-Chip XRAM
Figure 17.3. EMIF Operating Modes
Off-Chip
Memory
0xFFFF
0x0000
Rev. 1.4
.
EMI0CF[3:2] = 10
On-Chip XRAM
(Bank Select)
Off-Chip
Memory
Section “SFR Definition 17.3. EMI0TC:
0xFFFF
0x0000
EMI0CF[3:2] = 11
Off-Chip
Memory
0xFFFF
0x0000