C8051F130-GQR Silicon Laboratories Inc, C8051F130-GQR Datasheet - Page 310

• Manufacturer Part Number: C8051F130-GQR
• Description: IC 8051 MCU 128K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F13xr

Specifications of C8051F130-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to
“18.1. Ports 0 through 3 and the Priority Crossbar Decoder” on page 238
and configuring external I/O pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When
T0M is set, Timer 0 is clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source
selected by the Clock Scale bits in CKCON (see SFR Definition 23.3).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
/INT0 is logic-level 1. Setting GATE0 to ‘1’ allows the timer to be controlled by the external input signal /
INT0 (see
surements.
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal /INT1 is used with Timer 1.
310
TR0
X = Don't Care
0
1
1
1
/INT0
T0
Section “11.3.5. Interrupt Register Descriptions” on page 157
Crossbar
GATE0
X
0
1
1
Pre-scaled Clock
SYSCLK
GATE0
/INT0
Figure 23.1. T0 Mode 0 Block Diagram
X
X
0
1
TR0
0
1
Counter/Timer
Disabled
Disabled
Enabled
Enabled
CKCON
M
T
1
0
1
M
T
0
S
C
A
1
Rev. 1.4
S
C
A
0
G
A
E
T
1
C
T
1
/
M
T
1
1
TMOD
M
T
1
0
TCLK
G
A
T
E
0
C
T
0
/
M
T
0
1
M
T
0
0
(5 bits)
TL0
(8 bits)
TH0
), facilitating pulse width mea-
for information on selecting
TR1
TR0
TF1
TF0
IE1
IE0
IT1
IT0
Interrupt
Section